Patents by Inventor Ken Wadland
Ken Wadland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8789060Abstract: A method, computer program product and apparatus for utilizing simulated locking prior to starting concurrent execution are disclosed. The results of this simulated locking are used to define a canonical ordering which controls the order of execution and the degree of parallelism that can be used.Type: GrantFiled: December 27, 2007Date of Patent: July 22, 2014Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Charles W. Grant, Randall Lawson, Richard Allen Woodward, Jr., Sean Bergan
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Patent number: 8549459Abstract: In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented design constraints. Each of the routing engines have at least one action to operate on the design database to improve compliance of the circuit to a constraint. The CCM controls the overall routing process of the nets in the circuit and includes at least one director to invoke at least one of the routing engines to achieve compliance with one or more constraints.Type: GrantFiled: July 13, 2010Date of Patent: October 1, 2013Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Sean Bergan, Charles W. Grant, Glendine Kingsbury, Randall Lawson, Jelena Radumilo-Frankilin, Kota Sujan Reddy, Steve Russo, William Schilp, Davis Tsai, Keith Woodward, Richard Woodward, Jia Wu
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Patent number: 8510703Abstract: A method and system for auto-routing wiring within a PCB. In some embodiment, a first broad region within a first layer and a counterpart first broad region within a second layer are defined. The counterpart regions define a first broad via location. In some embodiments, the first and second broad via locations of the first and second layers can then be subdivided into a plurality of triangular regions. The triangular regions on the first and second layers can then be compared to more accurately locate an appropriate via location.Type: GrantFiled: April 1, 2005Date of Patent: August 13, 2013Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Richard Allen Woodward, Jr., Randall Lawson, Alan G Strelzoff, David Tsai, Steve Russo
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Patent number: 8479138Abstract: Techniques that can improve the efficiency of routing where connections are subject to elongation constraints. The design can be optimized by estimating elongation needed to meet constraints after an initial routing solution has been generated, but before elongation is actually applied to detailed paths. Paths can be re-routed at this earlier stage if it is determined that too much elongation, or too much elongation in crowded areas, will need to be added after the detail routing stage.Type: GrantFiled: September 25, 2009Date of Patent: July 2, 2013Assignee: Cadence Design Systems, Inc.Inventors: Randall Scott Lawson, Richard Allen Woodward, Jr., Brett Allen Neal, Ken Wadland
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Patent number: 8250514Abstract: A routing method for a multilayer circuit design layout that has a set of possible preferred local routing directions and a default preferred routing direction for each layer. The method receives a set of user specified constraints on routing directions for particular regions of the design layout. The method tessellates the available routing space into separate tiles and automatically defines a preferred local routing direction for each tile based on the user specified constraints. The set of user specified constraints includes user designated flows, locked etches, “etch keep-out” areas, user “planned” data, etc. A routing method for a multilayer design layout that receives a first set of user specified preferred routing directions for particular regions of the multilayer design layout. The method tessellates the available routing space into separate tiles and automatically defines a second preferred local routing direction for each tile based on the user specified preferred routing directions.Type: GrantFiled: July 13, 2006Date of Patent: August 21, 2012Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Randall Lawson, Jelena Radumilo-Franklin
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Patent number: 8191032Abstract: Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a process referred to as global constraint budgeting. An autorouter finds paths in the layout to satisfy the local constraints and ignores the global constraints. The local constraints are updated before each routing pass to ensure that routes are completed on individual direct connections while also satisfying the global constraint.Type: GrantFiled: July 9, 2009Date of Patent: May 29, 2012Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Sean Bergan, Randall Lawson, Keith Woodword, Richard Woodward
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Patent number: 8151239Abstract: Overloaded regions in the routing space of a physical network are resolved via a routing procedure composed of a topological routing phase and a geometric routing phase. The overloads are resolved in the topological routing phase where the constraints of routing are less prohibitive. Multiple topological transformations directed toward resolving the overloads are executed in the topological routing phase prior to a geometric arrangement being realized. The topological transformations may be applied concurrently by way of a multi-threaded embodiment of the invention.Type: GrantFiled: December 1, 2008Date of Patent: April 3, 2012Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, William Schilp
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Patent number: 8146042Abstract: An approach is provided for selectively optimizing a circuit design to be physical implemented. The approach includes generating a circuit routing solution in accordance with a plurality of constraints for parametric resources of the circuit design, with the constraints being defined respectively by a plurality of corresponding constraint instances. Each constraint instance variably indicates an effective constraining limit and degree of consumption for at least one of the parametric resources. At least one of the constraints is selectively adjusted by a predetermined over-constraining amount, and the circuit routing solution is preliminarily modified by applying at least one routing action selected responsive to the constraint adjustment. An automatic evaluation is then made of the potential impact upon constraint compliance.Type: GrantFiled: November 16, 2009Date of Patent: March 27, 2012Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Richard Woodward, Randall Lawson, Greg Horlick
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Patent number: 8086987Abstract: Overloaded regions in the routing space of a physical network are resolved via a routing procedure composed of a topological routing phase and a geometric routing phase. The overloads are resolved in the topological routing phase where the constraints of routing are less prohibitive. Multiple topological transformations directed toward resolving the overloads are executed in the topological routing phase prior to a geometric arrangement being realized. The topological transformations may be applied concurrently by way of a multi-threaded embodiment of the invention.Type: GrantFiled: July 21, 2011Date of Patent: December 27, 2011Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, William Schilp
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Patent number: 8082533Abstract: Overloaded regions in the routing space of a physical network are resolved via a routing procedure composed of a topological routing phase and a geometric routing phase. The overloads are resolved in the topological routing phase where the constraints of routing are less prohibitive. Multiple topological transformations directed toward resolving the overloads are executed in the topological routing phase prior to a geometric arrangement being realized. The topological transformations may be applied concurrently by way of a multi-threaded embodiment of the invention.Type: GrantFiled: July 21, 2011Date of Patent: December 20, 2011Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, William Schilp
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Patent number: 7937681Abstract: A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path independent of the solution paths for all other nets. The electrical and physical constraints of the system are initially ignored or greatly relaxed. Over each design iteration, the constraints are tightened until a complete, global, topological solution is found. Once a topological solution is found, it is converted into a geometric solution. In the event that no geometric solution exists for that topological solution, then the iteration process is resumed taking into consideration this additional information. The result is the ability to quickly autoroute highly-constrained PCB designs with minimal operator input.Type: GrantFiled: April 25, 2005Date of Patent: May 3, 2011Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Richard Allen Woodward, Jr., Randall Lawson, Walter Katz, Wiley Gillmor
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Patent number: 7793249Abstract: Automatic bundle filtering is provided to selectively configure a circuit design having a plurality of component terminals for physical implementation. A placement of components is established for a layout of the circuit design, and a plurality of connections to be routed between predetermined terminals of the components are defined for the layout, with a certain plurality of them selectively grouped into at least one candidate bundle. At least one filter is applied to the connections of each candidate bundle for responsive segregation according to a preselected connection discriminant into one or more updated bundle candidates. Each updated bundle candidate is preferably evaluated in accordance with at least one preselected bundling criteria to identify acceptable bundle candidates therefrom. Bundles corresponding to the acceptable bundle candidates are then generated.Type: GrantFiled: November 28, 2006Date of Patent: September 7, 2010Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Greg Horlick, Randall Lawson
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Patent number: 7761836Abstract: In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented design constraints. Each of the routing engines have at least one action to operate on the design database to improve compliance of the circuit to a constraint. The CCM controls the overall routing process of the nets in the circuit and includes at least one director to invoke at least one of the routing engines to achieve compliance with one or more constraints.Type: GrantFiled: October 11, 2006Date of Patent: July 20, 2010Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Sean Bergan, Charles W. Grant, Glendine Kingsbury, Randall Lawson, Jelena Radumilo-Franklin, Kota Sujan Reddy, Steve Russo, William Schilp, Davis Tsai, Keith Woodward, Richard Woodward, Jia Wu
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Patent number: 7620922Abstract: An approach is provided for selectively optimizing a circuit design, including generating a circuit routing solution according to a plurality of constraints for parametric resources of the circuit design, with the constraints being defined respectively by a plurality of corresponding constraint instances. Each constraint instance variably indicates an effective constraining limit and degree of consumption for at least one of the parametric resources. At least one of the constraints is selectively adjusted by a predetermined over-constraining amount, and the circuit routing solution is preliminarily modified by applying at least one routing action selected responsive to the constraint adjustment. The potential impact upon constraint compliance is evaluated, including generating a relative cost measure for the preliminary modification of the circuit routing solution, based at least partially upon each of the constraint instances.Type: GrantFiled: November 6, 2006Date of Patent: November 17, 2009Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Richard Woodward, Randall Lawson, Greg Horlick
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Patent number: 7594215Abstract: An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide an IC package routing solution. The global topological solution is used in conjunction with necessary design parameters to determine the optimal geometric routing solution which can include reassignment of IC nets and/or pin assignments and/or relocation of IC nets.Type: GrantFiled: April 21, 2005Date of Patent: September 22, 2009Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Joe Morrison, Julie Blumenthal
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Patent number: 7574686Abstract: Disclosed is a method, system, and computer program product for implementing a costed-search approach that supports concurrent operation on a multi-CPU system that enables out-of-order search evaluation that does not affect the final outcome of the algorithm. The algorithm is guaranteed to produce identical results when run as a single-threaded application on a single-CPU system. This allows a single regression test suite to be used to test single-threaded and multi-threaded versions of the product.Type: GrantFiled: August 11, 2006Date of Patent: August 11, 2009Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Randall Lawson, Charles W. Grant
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Patent number: 7562330Abstract: Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a process referred to as global constraint budgeting. An autorouter finds paths in the layout to satisfy the local constraints and ignores the global constraints. The local constraints are updated before each routing pass to ensure that routes are completed on individual direct connections while also satisfying the global constraint.Type: GrantFiled: November 6, 2006Date of Patent: July 14, 2009Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, Sean Bergan, Randall Lawson, Keith Woodword, Richard Woodward
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Patent number: 7536665Abstract: A mechanism is provided for the user to define a circuit design intent or strategy in the form of data that is stored with the design database. An autorouter then uses this guidance from the user to create a plan for routing the design. The user can then modify their guidance to the router until the results for the plan are acceptable. Using the planned flow, the autorouter can complete the design, creating detailed paths including etch segments and vias. Allowing such interaction with an autorouter significantly reduces the routing time and hence time-to-market.Type: GrantFiled: July 25, 2006Date of Patent: May 19, 2009Assignee: Cadence Design Systems, Inc.Inventors: Greg Horlick, Randall Lawson, Donald Morgan, Paul Musto, Joe Smedley, Ken Wadland, Richard Woodward, Sean Bergan, Walter M. Katz
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Patent number: 7464358Abstract: Overloaded regions in the routing space of a physical network are resolved via a routing procedure composed of a topological routing phase and a geometric routing phase. The overloads are resolved in the topological routing phase where the constraints of routing are less prohibitive. Multiple topological transformations directed toward resolving the overloads are executed in the topological routing phase prior to a geometric arrangement being realized. The topological transformations may be applied concurrently by way of a multi-threaded embodiment of the invention.Type: GrantFiled: January 26, 2006Date of Patent: December 9, 2008Assignee: Cadence Design Systems, Inc.Inventors: Ken Wadland, William Schilp
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Publication number: 20060242614Abstract: A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path independent of the solution paths for all other nets. The electrical and physical constraints of the system are initially ignored or greatly relaxed. Over each design iteration, the constraints are tightened until a complete, global, topological solution is found. Once a topological solution is found, it is converted into a geometric solution. In the event that no geometric solution exists for that topological solution, then the iteration process is resumed taking into consideration this additional information. The result is the ability to quickly autoroute highly-constrained PCB designs with minimal operator input.Type: ApplicationFiled: April 25, 2005Publication date: October 26, 2006Applicant: Cadence Design Systems, Inc.Inventors: Ken Wadland, Richard Woodward, Randall Lawson, Walter Katz, Wiley Gillmor