Patents by Inventor Ken Yamaguchi

Ken Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7132713
    Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: November 7, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshikazu Shimada, Hideo Sunami, Tatsuya Teshima, Toshiyuki Mine, Ken Yamaguchi
  • Publication number: 20060028853
    Abstract: According to one aspect of the present invention, there is provided a semiconductor device comprising a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.
    Type: Application
    Filed: October 4, 2005
    Publication date: February 9, 2006
    Inventors: Kenichi Osada, Takayuki Kawahara, Ken Yamaguchi, Yoshikazu Saito, Naoki Kitai
  • Patent number: 6977858
    Abstract: A semiconductor device comprises, a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: December 20, 2005
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Kenichi Osada, Takayuki Kawahara, Ken Yamaguchi, Yoshikazu Saito, Naoki Kitai
  • Publication number: 20050222600
    Abstract: An inverted capsular punch for cutting tissue. The inverted capsular punch has a punch end effector assembly comprising a fixed upper jaw and a movable lower jaw which is pivotably secured to the fixed jaw. The fixed upper jaw has a length greater than that of the movable lower jaw, and has an elongated, spoon-like configuration that allows gentle separation and retraction of the capsule from adjacent tissues and neurovascular structures in the joint. The movable lower jaw is provided with a plurality of cutting teeth or serrations that cut the capsule. The movable lower jaw is actuated by a pair of ring handles.
    Type: Application
    Filed: March 3, 2005
    Publication date: October 6, 2005
    Inventors: Ken Yamaguchi, Peter Dreyfuss, Robert Weber
  • Publication number: 20050203345
    Abstract: An articulating paddle elevator for manipulating tissue during arthroscopic procedures. The articulating elevator comprises a shaft, a proximal end, and a distal end provided with an articulating paddle. The paddle may be actuated by a switch and can articulate into a standard tip for traditional manipulation of tissue, or into a rotated or articulated position. In this manner, effective manipulation and retraction of tissue from the surgical site without tissue collapse may be achieved, allowing a surgeon to better visualize the internal condition of the arthroscopic site and speed up the overall procedure.
    Type: Application
    Filed: March 3, 2005
    Publication date: September 15, 2005
    Inventors: Ken Yamaguchi, Peter Dreyfuss, Robert Weber
  • Publication number: 20050106624
    Abstract: The present invention relates to a method of concentrating low molecular weight peptides in the supernatant of serum-free cultured cells, said method comprising allowing the peptides to bind to a strong cation exchanger under an acid condition, and eluting them under an alkali condition to concentrate the peptide. Furthermore, peptides having the amino acid sequence as set forth in SEQ ID NO: 1 or 2, and a method of screening cancer markers using antibody to these peptides, are disclosed.
    Type: Application
    Filed: August 5, 2002
    Publication date: May 19, 2005
    Inventors: Kazuki Sasaki, Kae Sato, Ken Yamaguchi
  • Publication number: 20050085919
    Abstract: The present invention relates to a set of tools and accessories used for properly positioning a stemmed humeral component, and/or a humeral stem provisional, within a canal in the humerus. The set of tools and accessories includes one or more fin clamps that are configured to be temporarily attached to a fin on the humeral component or the provisional; a ruler that is configured to be attached to the arm of the fin clamp, a fixation pin and pin driver configured to be used with the other tools for marking a position on the humerus; and one or more sleeves that are configured to slide over the stem of the humeral stem provisional to maintain it in the desired position.
    Type: Application
    Filed: December 18, 2003
    Publication date: April 21, 2005
    Inventors: Anitra Durand-Allen, Roy Wiley, Louis Bigliani, Evan Flatow, Ian Kelly, George McCluskey, Anthony Miniaci, Gregory Nicholson, Michael Pearl, Ken Yamaguchi
  • Patent number: 6780698
    Abstract: A method for producing a semiconductor device which comprises causing a dopant present in a semiconductor substrate to segregate in the surface of said semiconductor substrate, thereby forming a thin layer which has a higher dopant concentration than said substrate. The thin layer formed by segregation prevents punch-through which occurs as the result of miniaturization of MOSFET. This method permits economical delta doping without sacrificing the device characteristics.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: August 24, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Suwa, Tomihiro Hashizume, Ken Yamaguchi, Masaaki Fujimori
  • Patent number: 6781202
    Abstract: A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: August 24, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Ken Yamaguchi, Yoshiaki Takemura, Kenichi Osada, Masatada Horiuchi, Takashi Uchino
  • Publication number: 20040125676
    Abstract: According to one aspect of the present invention, there is provided a semiconductor device comprising a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.
    Type: Application
    Filed: December 8, 2003
    Publication date: July 1, 2004
    Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Osada, Takayuki Kawahara, Ken Yamaguchi, Yoshikazu Saito, Naoki Kitai
  • Publication number: 20030137012
    Abstract: A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.
    Type: Application
    Filed: November 26, 2002
    Publication date: July 24, 2003
    Inventors: Ken Yamaguchi, Yoshiaki Takemura, Kenichi Osada, Masatada Horiuchi, Takashi Uchino
  • Publication number: 20030119247
    Abstract: A method for producing a semiconductor device which comprises causing a dopant present in a semiconductor substrate to segregate in the surface of said semiconductor substrate, thereby forming a thin layer which has a higher dopant concentration than said substrate. The thin layer formed by segregation prevents punch-through which occurs as the result of miniaturization of MOSFET. This method permits economical delta doping without sacrificing the device characteristics.
    Type: Application
    Filed: July 15, 2002
    Publication date: June 26, 2003
    Inventors: Yuji Suwa, Tomihiro Hashizume, Ken Yamaguchi, Masaaki Fujimori
  • Publication number: 20030055215
    Abstract: A bovine- or human-derived calcium-binding protein with a prescribed amino acid sequence, a method for its production, and antibodies against the protein and uses thereof.
    Type: Application
    Filed: July 20, 2001
    Publication date: March 20, 2003
    Applicant: TONEN CORPORATION
    Inventors: Jiro Hitomi, Ken Yamaguchi, Tokujiro Yamamura, Tatsuji Kimura
  • Publication number: 20020139973
    Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
    Type: Application
    Filed: April 15, 2002
    Publication date: October 3, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshikazu Shimada, Hideo Sunami, Tatsuya Teshima, Toshiyuki Mine, Ken Yamaguchi
  • Patent number: 6329238
    Abstract: In a semiconductor memory device such as a DRAM, a conductive film is arranged on the rim portion of a isolation insulating film in opposition to a semiconductor substrate with a thin insulating film in between. This conductive film is electrically connected to a lower electrode of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: December 11, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Ken Yamaguchi, Shinichiro Kimura, Masatada Horiuchi, Tatsuya Teshima
  • Patent number: 6313267
    Abstract: A bovine- or human-derived calcium-binding protein with a prescribed amino acid sequence, a method for its production, and antibodies against the protein and uses thereof.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: November 6, 2001
    Assignee: Advanced Life Science Institute, Inc.
    Inventors: Jiro Hitomi, Ken Yamaguchi, Tokujiro Yamamura, Tatsuji Kimura
  • Patent number: 6211531
    Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: April 3, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshikazu Shimada, Hideo Sunami, Tatsuya Teshima, Toshiyuki Mine, Ken Yamaguchi
  • Patent number: 6187855
    Abstract: A rubbery adhesive composition wherein at least one adherend is a rubber composition including butadiene rubber as a rubber ingredient, characterized in that butadiene rubber is included as a rubber ingredient and 3˜20% by weight of the butadiene rubber is syndiotactic-1,2-polybutadiene. Thus, it is possible to enhance the strength of the rubbery adhesive composition itself to improve the adhesion property before and after vulcanization without damaging the adhesion property at the interface.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: February 13, 2001
    Assignee: Bridgestone Corporation
    Inventors: Yuichi Nagai, Ken Yamaguchi
  • Patent number: 6157055
    Abstract: In a semiconductor memory device such as a DRAM, a conductive film (1.11') is arranged on the rim portion of a isolation insulating film (1.2) in opposition to a semiconductor substrate (1.1) with a thin insulating film in between. This conductive film (1.11') is electrically connected to a lower electrode (1.11) of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: December 5, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Ken Yamaguchi, Shinichiro Kimura, Masatada Horiuchi, Tatsuya Teshima
  • Patent number: 6140407
    Abstract: This invention relates to a pneumatic tire coated with a water-based electrically conductive coating, in which the coating contains a carbon black having a nitrogen adsorption specific surface area (N.sub.2 SA) of 70 m.sup.2 /g-180 m.sup.2 /g and a dibutyl phtalate (DBP) absorption of 70 ml/100 g-180 ml/100 g, a surface active agent and a rubber ingredient.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: October 31, 2000
    Assignee: Bridgestone Corporation
    Inventors: Keizo Akutagawa, Yasuhiro Naito, Ken Yamaguchi