Abstract: A capacitive sensor has a structure in which first transparent electrode portions and second transparent electrode portions formed from crystalline indium tin oxide (ITO) are provided on a base material by patterning. A bridge wiring portion formed from amorphous indium zinc oxide (IZO) is provided on each two adjacent first transparent electrode portions and a link continuous to them, with an insulating layer intervening between the bridge wiring portion and the two first transparent electrode portions and link. These two adjacent second transparent electrode portions are electrically connected together by the bridge wiring portion. The thickness of the second transparent electrode portion TE and the thickness of the bridge wiring portion TB satisfy the following expressions: 0.28×TE+83 nm?TB?0.69×TE+105 nm; and 30 nm?TE?50 nm.

Abstract: A capacitive sensor has a structure in which first transparent electrode portions and second transparent electrode portions formed from crystalline indium tin oxide (ITO) are provided on a base material by patterning. A bridge wiring portion formed from amorphous indium zinc oxide (IZO) is provided on each two adjacent first transparent electrode portions and a link continuous to them, with an insulating layer intervening between the bridge wiring portion and the two first transparent electrode portions and link. These two adjacent second transparent electrode portions are electrically connected together by the bridge wiring portion. The thickness of the second transparent electrode portion TE and the thickness of the bridge wiring portion TB satisfy the following expressions: 0.28×TE+83 nm?TB?0.69×TE+105 nm; and 30 nm?TE?50 nm.

Abstract: An input device includes a plurality of first transparent electrodes, a plurality of second transparent electrodes, coupling portions each electrically connecting two adjacent second transparent electrodes of the second transparent electrodes, and bridge portions each electrically connecting two adjacent first transparent electrodes of the first transparent electrodes. The first and second transparent electrodes are arranged in directions orthogonal to each other and are formed of a material containing conductive nanowires. The bridge portions each include a bridge wiring part, an insulating layer, and a buffer layer. The buffer layer is disposed between each of the coupling portions and the insulating layer. The buffer layer is formed of a light-transmissive, inorganic oxide-based material.

Abstract: An input device includes a plurality of first transparent electrodes, a plurality of second transparent electrodes, coupling portions each electrically connecting two adjacent second transparent electrodes of the second transparent electrodes, and bridge portions each electrically connecting two adjacent first transparent electrodes of the first transparent electrodes. The first and second transparent electrodes are arranged in directions orthogonal to each other and are formed of a material containing conductive nanowires. The bridge portions each include a bridge wiring part, an insulating layer, and a buffer layer. The buffer layer is disposed between each of the coupling portions and the insulating layer. The buffer layer is formed of a light-transmissive, inorganic oxide-based material.

Abstract: It is possible to suppress a change in a resistance value caused by a potential of a semiconductor substrate 10 near a resistance element layer 13, a power line passing on or above the resistance element layer, or a signal line, without generating useless current or a distortion in a signal. A first conductive layer 15 biased by the potential of a first electrode 11 and a second conductive layer 16 biased by the potential of a second electrode 12 cover below the resistance element layer equally. A change in the resistance value caused by a potential difference between the resistance element layer and a neighboring semiconductor substrate 14 is cancelled by the first conductive layer and the second conductive layer covering at least one of above and below the resistance element layer with both ends biased, so the change in the resistance value is suppressed.

Abstract: There is provided a resistance element and an inverting buffer circuit to suppress a change in a resistance value caused by a potential of a semiconductor substrate in the neighborhood of the resistance element layer, a power line passing on or above the resistance element layer, or a signal line, without generating useless current or a distortion in a signal. In the resistance element 10, a resistance element layer 13 having a first electrode 11 and a second electrode 12 is formed on a semiconductor substrate 14. A first conductive layer 15 biased by the potential of the first electrode 11 and a second conductive layer 16 biased by the potential of the second electrode 12 cover below the resistance element layer 13 equally, so that a change in the resistance value is suppressed.

Abstract: A probe card includes a flat plate-shaped wiring board, a columnar base portion, and a thee-dimensional spiral contactor. The base portion is interposed between a wiring pattern of the wiring board and the bottom of the contactor.

Abstract: There is provided a digital switching amplifier capable of enhancing an S/N ratio at the time of a small signal output and reducing current consumption and electromagnetic interference (EMI).

Abstract: There is provided a digital switching amplifier capable of enhancing an S/N ratio at the time of a small signal output and reducing current consumption and electromagnetic interference (EMI).

Abstract: When a clock &phgr;1 is in high state, based on a digital signal, capacitive elements C11 to C1i are connected between a reference voltage Vr+ or Vr− and a sampling ground V1 to hold a charge corresponding to difference between the reference voltage and sampling ground V1 while capacitive elements C21 to C2i are connected between a reference voltage Vr+ or Vr− and a sampling ground V2 to hold a charge corresponding to difference between the reference voltage and sampling ground V2. When a clock &phgr;2 is in high state, the capacitive elements C11 to C1i and C21 to C2i are connected, in parallel with a feedback capacitive element Cfb, between an input terminal and output terminal of an operational amplifier 100. To obtain a D/A converter which operates at a lower supply voltage and produces output signals low in harmonic components and noise components.

Abstract: When a clock &phgr;1 is in high state, based on a digital signal, capacitive elements C11 to C1i are connected between a reference voltage Vr+ or Vr− and a sampling ground V1 to hold a charge corresponding to difference between the reference voltage and sampling ground V1 while capacitive elements C21 to C2i are connected between a reference voltage Vr+ or Vr− and a sampling ground V2 to hold a charge corresponding to difference between the reference voltage and sampling ground V2. When a clock &phgr;2 is in high state, the capacitive elements C11 to C1i and C21 to C2i are connected, in parallel with a feedback capacitive element Cfb, between an input terminal and output terminal of an operational amplifier 100.

Abstract: In order to provide an electronic circuit board capable of preventing the breakdown voltage of a capacitor element from dropping and excellent in high frequency performance, a positive type photoresist is spin-coated over the surface of an alumina substrate and is exposed to light and developed to form an insulating layer partially, followed by formation of a capacitor element by successively stacking a lower electrode, a dielectric layer and an upper electrode over this insulating layer, further followed by formation of a resistance element, an inductor element and a transmission line, each in a filmy state, over the surface of the alumina substrate.

Abstract: In order to provide an electronic circuit board capable of preventing the breakdown voltage of a capacitor element from dropping and excellent in high frequency performance, a positive type photoresist is spin-coated over the surface of an alumina substrate and is exposed to light and developed to form an insulating layer partially, followed by formation of a capacitor element by successively stacking a lower electrode, a dielectric layer and an upper electrode over this insulating layer, further followed by formation of a resistance element, an inductor element and a transmission line, each in a filmy state, over the surface of the alumina substrate.

Abstract: A thermal head including a temperature keeping layer disposed on a substrate, a plurality of heat generating elements formed on the temperature keeping layer, a plurality of individual electrodes connected to the corresponding heat generating elements, a common electrode connected to the heat generating elements, respectively. Each heat generating element includes a heat generating portion formed between one of the individual electrodes and the common electrode. Each of the individual electrodes and the common electrode have a dual layered structure including a lower electrode and an upper electrode, the lower electrode being formed between the temperature keeping layer and one of the heat generating elements, and the upper electrode being formed above the heat generating element.

Abstract: A semiconductor device of the present invention accommodates a large semiconductor chip in a downsized package without impairing its reliability. The semiconductor chip is bonded on a relatively small die pad. Common inner leads and a plurality of inner leads are disposed opposite and spaced from the semiconductor chip by a gap ranging from 0.1 mm to 0.4 mm and the gap between the semiconductor chip and the common inner leads and the plurality of inner leads is filled with a resin which forms part of a resin package.

Abstract: A semiconductor device of the present invention accommodates a large semiconductor chip in a downsized package without impairing its reliability. The semiconductor chip is bonded on a relatively small die pad. Common inner leads and a plurality of inner leads are disposed opposite and spaced from the semiconductor chip by a gap ranging from 0.1 mm to 0.4 mm and the gap between the semiconductor chip and the common inner leads and the plurality of inner leads is filled with a resin which forms pan of a resin package.