Patents by Inventor Ken Yanai
Ken Yanai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960967Abstract: An information processing system, which determines a partial area used in an erectness determination which determines whether a determination target image is erect based on a determination feature in the partial area in an image having a predetermined format and a position of the partial area in a state in which the image having the predetermined format is erect, includes processor to receive input of a plurality of learning images having the predetermined format, extract area common to the plurality of learning images in an erect state as a candidate for the partial area, determine common area reliability indicative of a degree to which the candidate for the partial area is suitable as the partial area used in the erectness determination, and determine the partial area used in the erectness determination from the candidate for the partial area, based on the common area reliability.Type: GrantFiled: April 26, 2021Date of Patent: April 16, 2024Assignee: PFU LIMITEDInventors: Katsuhiro Hattori, Yutaka Harano, Tomoaki Wada, Ken Yanai
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Publication number: 20240105365Abstract: An object of the present disclosure is to provide a multilayer varistor with the ability to reduce the chances of causing crosstalk between external terminals. Inside a sintered body having the shape of a rectangular parallelepiped, of which the longitudinal axis is aligned with a first direction, a first facing portion and a second facing portion are provided to interpose a third facing portion between themselves. At least one of a first side surface or a second side surface is provided with a first external electrode connected to the first facing portion, a second external electrode connected to the second facing portion, and a third external electrode and a fourth external electrode connected to the third facing portion. In the first direction, the first external electrode and the second external electrode are interposed between the third external electrode and the fourth external electrode.Type: ApplicationFiled: February 18, 2022Publication date: March 28, 2024Inventors: Yuto AKIYAMA, Masashi TAKAMURA, Ken YANAI
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Patent number: 11853844Abstract: An information processing apparatus includes a processor to store a determination feature in a predetermined partial area in an image having a predetermined format and a position of the partial area in a state in which the predetermined format image is erect, and determine whether a feature corresponding to the determination feature is present at a position in an at least one input determination target image corresponding to the position of the partial area in the predetermined format image to thereby determine whether the determination target image is erect.Type: GrantFiled: April 14, 2021Date of Patent: December 26, 2023Assignee: PFU LIMITEDInventors: Katsuhiro Hattori, Tomoaki Wada, Ken Yanai
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Patent number: 11791072Abstract: A laminated varistor includes a varistor layer, a first internal electrode provided on an upper surface of the varistor layer, a second internal electrode provided on a lower surface of the varistor layer and facing the first internal electrode across the varistor layer in upward and downward directions, a first external electrode provided on a first side surface of the varistor layer and electrically connected to the first internal electrode, and a second external electrode provided on a second side surface of the varistor layer and electrically connected to the second internal electrode. The first internal electrode is extended from the first external electrode in a first extension direction. The first internal electrode includes first electrode strips arranged in a first arrangement direction perpendicular to the first extension direction and spaced apart from one another. This laminated varistor has improved surge-resistant characteristics.Type: GrantFiled: July 16, 2020Date of Patent: October 17, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Michiya Watanabe, Naoki Mutou, Ken Yanai
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Publication number: 20230326636Abstract: A multilayer varistor includes a sintered body and a first internal electrode, a second internal electrode, a third internal electrode, and a fourth internal electrode which are disposed in the sintered body. The first internal electrode, the second internal electrode, the third internal electrode, and the fourth internal electrode are arranged in an order of the first internal electrode, the third internal electrode, the fourth internal electrode, and the second internal electrode from a side of a first main face. The third internal electrode and the fourth internal electrode are electrically connected to each other. At least part of the first internal electrode and at least part of the third internal electrode overlap each other when viewed in a third direction. At least part of the second internal electrode and at least part of the fourth internal electrode overlap each other when viewed in the third direction.Type: ApplicationFiled: March 10, 2023Publication date: October 12, 2023Inventors: Masashi TAKAMURA, Yuto AKIYAMA, Ken YANAI
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Publication number: 20230274864Abstract: A multilayer varistor according to the present disclosure includes: a sintered compact having, on a surface thereof, at least one planar portion and at least one corner portion; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the at least one planar portion and the at least one corner portion of the sintered compact at least partially; and an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode. The high-resistivity layer includes: a first high-resistivity layer covering the at least one planar portion; and a second high-resistivity layer covering the at least one corner portion. The first high-resistivity layer has a larger average thickness than the second high-resistivity layer.Type: ApplicationFiled: February 23, 2023Publication date: August 31, 2023Inventors: Yuto AKIYAMA, Ken YANAI, Masashi TAKAMURA, Yuji YAMAGISHI, Ryosuke USUI
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Publication number: 20230274863Abstract: A multilayer varistor according to the present disclosure includes; a sintered compact; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the sintered compact at least partially; and an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode. The high-resistivity layer includes a thinner region having a smaller thickness than a surrounding region that surrounds the thinner region.Type: ApplicationFiled: February 23, 2023Publication date: August 31, 2023Inventors: Yuto AKIYAMA, Ken YANAI, Ryosuke USUI, Yuji YAMAGISHI, Masashi TAKAMURA
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Publication number: 20230245806Abstract: A method for manufacturing a multilayer varistor includes: a first step including providing a multilayer stack in which a plurality of green sheet layers, each containing a Zn oxide powder as a main component and a Pr oxide powder as a sub-component, and a plurality of internal electrode paste layers, each containing a Pd powder, are alternately stacked; and a second step including forming a sintered compact, including an internal electrode inside, by baking the multilayer stack. The second step includes: a first sub-step including baking the multilayer stack by setting an oxygen concentration in an atmosphere at 1000 ppm by volume or less while increasing a temperature from 500° C. to 800° C.; and a second sub-step including baking, after the first sub-step, the multilayer stack by setting the oxygen concentration in the atmosphere at 1000 ppm by volume or more while increasing the temperature to a maximum allowable temperature.Type: ApplicationFiled: January 19, 2023Publication date: August 3, 2023Inventors: Naoki MUTOU, Yoshiyuki SATOU, Yuji YAMAGISHI, Ken YANAI
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Publication number: 20230207159Abstract: A multilayer varistor includes: a sintered compact; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the sintered compact at least partially and containing element Si; and an external electrode arranged to cover the high-resistivity layer partially, electrically connected to the internal electrode, and containing silver as a main component thereof. A ratio of a total mass of the alkali metals and the alkaline earth metals to a mass of the element Si in a surface region of the high-resistivity layer is equal to or less than 0.6.Type: ApplicationFiled: December 19, 2022Publication date: June 29, 2023Inventors: Yuto AKIYAMA, Ken YANAI, Ryosuke USUI, Yuji YAMAGISHI
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Publication number: 20230197321Abstract: A multilayer varistor of the present disclosure includes a sintered body, a first internal electrode, a second internal electrode, a first external electrode, a second external electrode, and a high-resistance layer. The first internal electrode and the second internal electrode are disposed in the sintered body. The first external electrode is disposed on a surface of the sintered body and is electrically connected to the first internal electrode. The second external electrode is disposed on the surface of the sintered body and is electrically connected to the second internal electrode. The high-resistance layer covers at least part of the surface of the sintered body, and the high-resistance layer has a surface having a plurality of cracks.Type: ApplicationFiled: December 12, 2022Publication date: June 22, 2023Inventors: Yuto AKIYAMA, Ryosuke USUI, Ken YANAI
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Publication number: 20230134880Abstract: It is aimed to provide a laminated varistor capable of reducing stray capacitance to occur between an internal electrode and an external electrode, and also capable of reducing a variation in the stray capacitance due to a variation in the external electrode. A laminated varistor of the present disclosure has external electrodes on first end surface, second end surface, and first side surface of sintered body. No external electrode is provided on second side surface opposite to first side surface. Varistor regions in which internal electrodes overlap each other in a laminating direction are provided at positions closer to second side surface than to first side surface.Type: ApplicationFiled: September 24, 2020Publication date: May 4, 2023Inventors: SAYAKA MATSUMOTO, KEN YANAI, MASASHI TAKAMURA, MASAYA HATTORI, TOMOMITSU MURAISHI
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Publication number: 20230104285Abstract: A stacked varistor having a small variation in electrostatic capacitance is obtained. The stacked varistor includes first internal electrode projection extending from third internal electrode toward first end surface between first side surface and first varistor region, and second internal electrode projection extending from third internal electrode toward second end surface between first side surface and second varistor region . First internal electrode projection extends closer to first end surface than a line connecting point closest to first end surface of first varistor region and point closest to first end surface of third external electrode is. Second internal electrode projection extends closer to second end surface than a line connecting point closest to second end surface of second varistor region and point closest to second end surface of third external electrode is.Type: ApplicationFiled: March 18, 2021Publication date: April 6, 2023Inventors: MASASHI TAKAMURA, KEN YANAI, SAYAKA WATANABE, TOMOMITSU MURAISHI
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Publication number: 20230079197Abstract: A multilayer varistor has a stack structure including a plurality of layers stacked in a third direction. The multilayer varistor includes a first internal electrode electrically connected to a first external electrode, a second internal electrode electrically connected to the second external electrode, and a third internal electrode electrically connected to the third external electrode. The first internal electrode is disposed between the second internal electrode and the third internal electrode in the third direction.Type: ApplicationFiled: December 17, 2021Publication date: March 16, 2023Inventors: Masashi TAKAMURA, Sayaka WATANABE, Takeshi FUJII, Ken YANAI, Yuto AKIYAMA
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Publication number: 20220310291Abstract: A sintered body that includes semiconductor ceramic layers and an internal electrode which are alternately stacked on one another is prepared. A first external electrode is formed on a side surface of the sintered body such that the first external electrode is connected to the internal electrode. An insulating layer is formed on a surface of the sintered body by applying a glass coating over an entire of the sintered body having the formed first external electrode. The insulating layer is exposed from the first external electrode. A second external electrode is formed on the first external electrode. This method provides the produced multilayer electronic component with a stable electric connection between the internal electrodes and the external electrodes.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Ken YANAI, Tomokazu YAMAGUCHI, Yuji YAMAGISHI, Naoki MUTOU, Sayaka MATSUMOTO, Ryosuke USUI
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Publication number: 20220270791Abstract: A laminated varistor includes a varistor layer, a first internal electrode provided on an upper surface of the varistor layer, a second internal electrode provided on a lower surface of the varistor layer and facing the first internal electrode across the varistor layer in upward and downward directions, a first external electrode provided on a first side surface of the varistor layer and electrically connected to the first internal electrode, and a second external electrode provided on a second side surface of the varistor layer and electrically connected to the second internal electrode. The first internal electrode is extended from the first external electrode in a first extension direction. The first internal electrode includes first electrode strips arranged in a first arrangement direction perpendicular to the first extension direction and spaced apart from one another. This laminated varistor has improved surge-resistant characteristics.Type: ApplicationFiled: July 16, 2020Publication date: August 25, 2022Inventors: MICHIYA WATANABE, NAOKI MUTOU, KEN YANAI
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Patent number: 11387023Abstract: A sintered body that includes ceramic layers and an internal electrode which are alternately stacked on one another is prepared. A first external electrode is formed on a side surface of the sintered body such that the first external electrode is connected to the internal electrode. An insulating layer is formed on a surface of the sintered body by applying a glass coating over an entire of the sintered body having the formed first external electrode. The insulating layer is exposed from the first external electrode. A second external electrode is formed on the first external electrode. This method provides the produced multilayer electronic component with a stable electric connection between the internal electrodes and the external electrodes.Type: GrantFiled: September 19, 2018Date of Patent: July 12, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Ken Yanai, Tomokazu Yamaguchi, Yuji Yamagishi, Naoki Mutou, Sayaka Matsumoto, Ryosuke Usui
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Publication number: 20210390326Abstract: An information processing system, which determines a partial area used in an erectness determination which determines whether a determination target image is erect based on a determination feature in the partial area in an image having a predetermined format and a position of the partial area in a state in which the image having the predetermined format is erect, includes processor to receive input of a plurality of learning images having the predetermined format, extract area common to the plurality of learning images in an erect state as a candidate for the partial area, determine common area reliability indicative of a degree to which the candidate for the partial area is suitable as the partial area used in the erectness determination, and determine the partial area used in the erectness determination from the candidate for the partial area, based on the common area reliability.Type: ApplicationFiled: April 26, 2021Publication date: December 16, 2021Applicant: PFU LIMITEDInventors: Katsuhiro Hattori, Yutaka Harano, Tomoaki Wada, Ken Yanai
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Publication number: 20210335006Abstract: An information processing apparatus includes a processor to store a determination feature in a predetermined partial area in an image having a predetermined format and a position of the partial area in a state in which the predetermined format image is erect, and determine whether a feature corresponding to the determination feature is present at a position in an at least one input determination target image corresponding to the position of the partial area in the predetermined format image to thereby determine whether the determination target image is erect.Type: ApplicationFiled: April 14, 2021Publication date: October 28, 2021Applicant: PFU LIMITEDInventors: Katsuhiro Hattori, Tomoaki Wada, Ken Yanai
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Publication number: 20200194151Abstract: A sintered body that includes semiconductor ceramic layers and an internal electrode which are alternately stacked on one another is prepared. A first external electrode is formed on a side surface of the sintered body such that the first external electrode is connected to the internal electrode. An insulating layer is formed on a surface of the sintered body by applying a glass coating over an entire of the sintered body having the formed first external electrode. The insulating layer is exposed from the first external electrode. A second external electrode is formed on the first external electrode. This method provides the produced multilayer electronic component with a stable electric connection between the internal electrodes and the external electrodes.Type: ApplicationFiled: September 19, 2018Publication date: June 18, 2020Inventors: KEN YANAI, TOMOKAZU YAMAGUCHI, YUJI YAMAGISHI, NAOKI MUTOU, SAYAKA MATSUMOTO, RYOSUKE USUI
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Patent number: 5376466Abstract: A cermet blade member including a cermet substrate is provided which consists essentially of: 0.2% by weight to 8% by weight of a binder phase of at least one binder metal of cobalt and nickel; 5% by weight to 30% by weight of a first hard dispersed phase of at least one material of zirconia and a stabilized zirconia; and the remainder of a second hard dispersed phase of at least one metal carbo-nitride. The metal of the above-mentioned metal carbo-nitride is selected from metals in Group IVA in a periodic table. In addition, a cermet blade member including the cermet substrate and a hard coating layer formed on the surface of the cermet substrate is provided. The hard coating layer consists of at least one layer of a compound selected from a titanium carbide, a titanium nitride, a titanium carbo-nitride, titanium carbo-oxide represented by TiCO, titanium carbo-oxi-nitride represented by TiCNO and an aluminum oxide.Type: GrantFiled: October 14, 1992Date of Patent: December 27, 1994Assignee: Mitsubishi Materials CorporationInventors: Takashi Koyama, Susumu Uchida, Ken Yanai