Abstract: Provided is a technology for realizing detection of unidentified water without using a flowmeter. One embodiment of the present invention pertains to an unidentified water detection device having: a feature quantity extraction unit which extracts, from acoustic data including running water sound, an acoustic feature quantity pattern that indicates temporal changes in an acoustic feature quantity; and an unidentified water prediction unit which, using a machine learning model learned from the acoustic feature quantity pattern extracted from data that contains acoustic data including running water sound during lack of rainfall and/or acoustic data of running water sound under a condition different from during lack of rainfall, predicts the presence/absence of unidentified water from the acoustic feature quantity pattern of acoustic data of a prediction object, wherein the acoustic feature quantity pattern indicates temporal changes in the acoustic feature quantity in terms of time period and day of the week.

Abstract: A single-wire interface communication system is capable of providing both electrical communication of signals and power between devices coupled to the system. Coupled to the single-wire interface is at least one target device which contains a PMOS transistor, a charge storage device, an inverter controlling the PMOS transistor, and a target device function. The charge storage device provides power to the target device function and to the inverter. The PMOS transistor receives power from the single-wire interface at a power-supply voltage level and charges the charge storage device to the same level. Non-communication periods produce a charging period sufficient for the charge storage device to attain the power-supply voltage level.

Abstract: A single-wire interface communication system is capable of providing both electrical communication of signals and power between devices coupled to the system. Coupled to the single-wire interface is at least one target device which contains a PMOS transistor, a charge storage device, an inverter controlling the PMOS transistor, and a target device function. The charge storage device provides power to the target device function and to the inverter. The PMOS transistor receives power from the single-wire interface at a power-supply voltage level and charges the charge storage device to the same level. Non-communication periods produce a charging period sufficient for the charge storage device to attain the power-supply voltage level.

Abstract: A charge pump generates a voltage higher than an intermediate voltage and a regulator circuit provides a first regulated voltage higher than the intermediate voltage. A second stage includes a regulator stage using the first voltage to provide the intermediate voltage from the first voltage. A charge pump provides a pump output voltage. The pump output voltage is divided and the divided voltage is presented to a first comparator that compares it with a reference voltage. The first comparator drives the gate of a first MOS transistor to regulate the pump output voltage to a regulated voltage related to the reference voltage. The regulated voltage is presented to a second comparator that compares it with the reference voltage. The second comparator drives the gate of a second MOS transistor to downconvert the regulated output voltage to an intermediate voltage related to the reference voltage.