Abstract: A method of modeling a scenario for use with live data in a production database may include selecting the scenario. The live data can be stored in the production database on a first computing resource, and production scenarios can be stored and executed on the live data using the first computing resource. The method may also include identifying a subset of the live data that are affected by the scenario, copying the subset to a second computing resource to create modeling data, running the scenario on the modeling data using the second computing resource, causing a display device to provide an output comprising a result of the scenario on the modeling data, receiving an input indicating that the scenario is approved, and storing the scenario with the plurality of production scenarios for use on the first computing resource.

Abstract: A Flash memory controller for a system having first and second microcontrollers configured to perform first and second functions, and further having a Flash memory medium shared by the two microcontrollers, includes first and second execute-in-place cache controllers respectively configured to cache program code retrieved from the Flash memory for execution by the respective microcontrollers. A cache-miss arbiter controls access by the microcontrollers to the Flash memory on occurrence of a cache miss in one of the cache controllers. The arbiter may allow aborting of a first fetching operation on behalf of one of the microcontrollers upon receipt of a fetch request from the other microcontroller if the first fetching operation has retrieved a desired data unit and a threshold amount of data. The Flash memory controller may also include a decryption engine configured to decrypt encrypted program code. The decryption mode is determined from address ranges.

Abstract: A Flash memory controller for a system having first and second microcontrollers configured to perform first and second functions, and further having a Flash memory medium shared by the two microcontrollers, includes first and second execute-in-place cache controllers respectively configured to cache program code retrieved from the Flash memory for execution by the respective microcontrollers. A cache-miss arbiter controls access by the microcontrollers to the Flash memory on occurrence of a cache miss in one of the cache controllers. The arbiter may allow aborting of a first fetching operation on behalf of one of the microcontrollers upon receipt of a fetch request from the other microcontroller if the first fetching operation has retrieved a desired data unit and a threshold amount of data. The Flash memory controller may also include a decryption engine configured to decrypt encrypted program code. The decryption mode is determined from address ranges.

Abstract: A network device including first, second and third transceiver modules, which transmit or receive first, second and third data signals. A control module generates a mask signal based on a parameter of the first, second or third transceiver modules. The mask signal includes a direction bit and a first channel that identifies a first frequency. The direction bit indicates a range of frequencies. Transmission on the first frequency and some of the range of frequencies causes desensitization of the second data signal. A hopping module, based on a clock signal, selects a second channel for the third data signal. An output module, based on the mask signal and the second channel, generates an overlap signal indicating whether potential desensitization of the first or third data signal exists. An arbitration module, based on the overlap signal, provides the first or third transceiver module access to a first or second switch module.

Abstract: A power management device of a wireless communication assembly receives respective signals indicative of respective voltage supply levels required by respective hardware devices among a plurality of hardware devices of the wireless communication assembly, where the respective required voltage supply levels vary over time. The power management device selects a voltage supply level corresponding to a maximum voltage supply level indicated by the respective received signals, adjusts, based on the selected supply voltage level, a supply voltage supplied to the wireless communication assembly so that the selected voltage supply level is supplied to all of the hardware devices of the wireless communication assembly.

Abstract: A device including a first transceiver configured to transmit and receive, using a first antenna, according to a first communication protocol, a second transceiver configured to transmit and receive, using a second antenna, according to the first communication protocol, and a third transceiver configured to transmit and receive, using the second antenna, according to a second communication protocol. A controller is configured to select between a first mode where the first, second, and third transceivers are configured to respectively communicate using the first and second antennas at a same time, and a second mode where the first, second, and third transceivers are configured to respectively communicate using the first and second antennas at different times. In the first mode and the second mode, the controller is further configured to selectively allow the second transceiver to transmit and receive using the second antenna at a same time as the third transceiver.

Abstract: A power management device of a wireless communication assembly receives respective signals indicative of respective voltage supply levels required by respective hardware devices among a plurality of hardware devices of the wireless communication assembly, where the respective required voltage supply levels vary over time. The power management device selects a voltage supply level corresponding to a maximum voltage supply level indicated by the respective received signals, adjusts, based on the selected supply voltage level, a supply voltage supplied to the wireless communication assembly so that the selected voltage supply level is supplied to all of the hardware devices of the wireless communication assembly.

Abstract: In a method for dynamically adjusting power consumption of a wireless assembly in a communication device a first signal indicative of activity of a first wireless interface unit and a second signal indicative of activity of a second wireless interface unit are received at a dynamic power management unit. The first wireless interface unit configured to operate according to a first communication protocol. The second wireless interface unit configured to operate according to a second communication protocol. The second communication protocol is different than the first communication protocol. A supply voltage level needed to support the activity of the first wireless interface unit and the activity second wireless interface unit is supported based on the first signal and the second signal. A supply voltage supplied to the wireless assembly is adjusted based on the supply voltage level.

Abstract: Systems and techniques relating to wireless communications are described. A described technique includes performing, at a wireless communication device, an arbitration among multiple different wireless radio technologies, which collectively use two or more radio resources of the wireless communication device, to produce an arbitration result; and operating the two or more radio resources in accordance with the arbitration result. Performing the arbitration can include performing a first level arbitration between a request associated with a first technology of the multiple different wireless radio technologies and a request associated with a second technology of the multiple different wireless radio technologies to produce a first level result; and performing a second level arbitration to produce a second level result when indicated by the first level result. The arbitration result can be based on the first level result and the second level result, if any.

Abstract: A circuit processes requests to access an antenna, the requests from a plurality of wireless communication protocols components including (i) a first wireless communication protocol component and (ii) a second wireless communication protocol component. The circuit causes a switch to provide the second wireless communication component with access to the antenna while the circuit is in a power saving mode of operation, and, upon the circuit exiting the power saving mode of operation, determines whether the second wireless communication component is utilizing the antenna. The circuit, upon the circuit exiting the power saving mode of operation, applies a first set of arbitration rules when it is determined that the second wireless communication component is utilizing the antenna, and, upon the circuit exiting the power saving mode of operation, applies a second set of arbitration rules when it is determined that the second wireless communication component is not utilizing the antenna.

Abstract: According to one embodiment, an apparatus includes a first processing unit operating according to a first clock, a second processing unit operating according to a second clock running separately from the first clock, and a synchronization controller coupled to the first communication unit and the second communication unit. The synchronization controller is configured to (i) cause the first communication unit to generate a first indication of time at which the first processing unit transmits a signal to the second processing unit, according to the first clock, (ii) cause the second processing unit to generate a second indication of time at which the second processing unit receives the signal, according to the second clock, and (iii) determine an offset between the first clock and the second clock based on the first indication of time and the second indication of time.

Abstract: Methods and systems are provided for steering network packets. According to one embodiment, a dynamically configurable steering table is stored within a memory of each network interface of a networking routing/switching device. The steering table represents a mapping that logically assigns each of the network interfaces to one of multiple packet processing resources of the network routing/switching device. The steering table has contained therein information indicative of a unique identifier/address of the assigned packet processing resource. Responsive to receiving a packet on a network interface, the network interface performs Layer 1 or Layer 2 steering of the received packet to the assigned packet processing resource by retrieving the information indicative of the unique identifier/address of the assigned packet processing resource from the steering table based on a channel identifier associated with the received packet and the received packet is processed by the assigned packet processing resource.

Abstract: A radio frequency front-end includes a first path, second path, and third path each coupled between an antenna and a transceiver. The first path is configured to convey WLAN signals from the transceiver to the antenna for transmission. The second path is configured to convey received Bluetooth signals and received WLAN signals from the antenna to the transceiver. The third path is configured to convey Bluetooth signals from the transceiver to the antenna for transmission when a WLAN link is active and not in a power save state, and is configured to convey received Bluetooth signals from the antenna to the transceiver, and Bluetooth signals from the transceiver to the antenna for transmission, when the WLAN link is either inactive or in the power save state.

Abstract: A web service for automatically determining accounting entries that are affected by the deletion of a journal, formulating reverse accounting entries, and sending the reverse entries back to the source system is described. The service can use transaction identification keys to map and track which accounting entries are affected by the deletion of the journal. The web service can use extensible markup language (XML) among other formats.

Abstract: Methods, systems and computer program products are described for transferring aggregated data packets over an I/O interface from a host to a multiport embedded device. For example, a method includes receiving, by the device from the host, a single write command that (i) specifies two or more ports from among multiple ports of the device, and (ii) includes two or more data packets to be respectively written to the specified ports. The multiple ports of the device are mapped to corresponding locations of memory of the device. The method further includes saving, by the device in response to the single write command, the two or more data packets at two or more memory locations to which the specified ports are mapped. Additionally, the method includes sending, upon saving the data packets, a single notification to the host indicating that the device is ready to receive another write command.

Abstract: A coexistence system including first and second transceiver modules and an arbitration module. The first transceiver module generates a first request signal and operates according to a first wireless communication standard. The first request signal requests transmission or reception for the first transceiver module. The second transceiver module generates a second request signal and an overlap signal and operates according to a second wireless communication standard. The second request signal requests permission for the second transceiver module to transmit or receive. The overlap signal indicates whether desensitization is expected of a frequency of the first transceiver module or a frequency of the second transceiver module. The arbitration module (i) based on the overlap signal, arbitrates the first and second request signals, and (ii) based on the arbitration of the first and second request signals, selectively connect antennas to the first and second transceiver modules in one multiple configurations.

Abstract: The present disclosure describes apparatuses and techniques for low-noise regulation of battery power. In some aspects an indication of a voltage level of a battery supplying power to a linear regulator is received, an output voltage level is determined for the linear regulator that permits the linear regulator to operate in an active condition in which noise of the power supplied by the battery is mitigated, and the linear regulator is configured to output the regulated power at the output voltage level effective to provide low-noise regulated power for components of a device.

Abstract: Systems, methods, and other embodiments associated with performing arbitration among a plurality of driver circuits in a communication device are described. According to one embodiment, an apparatus includes a first source configured to transmit first packets and a second source configured to transmit second packets. The arbiter logic is configured to input a thermal management mode that is selected based, at least in part, on a thermal consequence of simultaneous transmission of packets from the first source and the second source. The arbiter logic is configured to select either i) the first packets, ii) the second packets, or iii) both the first packets and the second packets for transmission based, at least in part, on the thermal management mode input by the arbiter logic.

Abstract: In a method for controlling a wireless device assembly coupled to a host assembly, a clock signal is received at the wireless device assembly from the host assembly. The clock signal is supplied to an interface module in the wireless device assembly during a power save mode of the wireless device assembly and is used to operate the interface module. An initialization command is received at the wireless device assembly from the host assembly and is detected with the interface module. In response to detecting the initialization command, at least a portion of the wireless device assembly, other than the interface module, is activated.

Abstract: Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies.