Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.

Abstract: A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.

Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.

Abstract: A method includes providing a structure that includes a semiconductor substrate, an epitaxial source/drain feature over the semiconductor substrate, and one or more dielectric layers over the epitaxial source/drain feature; etching a hole into the one or more dielectric layer to expose a portion of the epitaxial source/drain feature; forming a silicide layer over the portion of the epitaxial source/drain feature; forming a conductive barrier layer over the silicide layer; and applying a plasma cleaning process to at least the conductive barrier layer, wherein the plasma cleaning process uses a gas mixture including N2 gas and H2 gas and is performed at a temperature that is at least 300° C.

Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.

Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.

Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

Abstract: A method includes providing a structure that includes a semiconductor substrate, an epitaxial source/drain feature over the semiconductor substrate, and one or more dielectric layers over the epitaxial source/drain feature; etching a hole into the one or more dielectric layer to expose a portion of the epitaxial source/drain feature; forming a silicide layer over the portion of the epitaxial source/drain feature; forming a conductive barrier layer over the silicide layer; and applying a plasma cleaning process to at least the conductive barrier layer, wherein the plasma cleaning process uses a gas mixture including N2 gas and H2 gas and is performed at a temperature that is at least 300° C.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.