Patents by Inventor Kenan Yu
Kenan Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240086605Abstract: A method for providing an IC design is disclosed. The method includes receiving and synthesizing a behavioral description of an IC design; generating, based on the synthesized behavioral description, a layout for the IC design; performing at least a timing analysis on the layout; accessing, based on the timing analysis, a first cell library including a plurality of transistor-based cells, each having one or more transistors and associated with a respective first delay value; accessing, based on the timing analysis, a second cell library including a plurality of non-transistor-based cells, each having no transistor and associated with a respective second delay value; and updating the layout by at least one of inserting one or more of the plurality of transistor-based cells or inserting one or more of the plurality of non-transistor-based cells.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kenan Yu, Qingwen Deng
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Publication number: 20240076342Abstract: De novo designed polypeptides that bind to IL-2 receptor ??c heterodimer (IL-2R??c), IL-4 receptor ??c heterodimer (IL-4R??c), or IL-13 receptor ? subunit (IL-13R?) are disclosed, as are methods for using and designing the polypeptides.Type: ApplicationFiled: March 21, 2023Publication date: March 7, 2024Inventors: Daniel Adriano Silva Manzano, Shawn Yu, Umut Ulge, David Baker, Kenan Christopher Garcia, Jamie Spangler, Carl Walkey, Alfredo Quijano Rubio, Kevin Jude, Brian Weitzner
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Patent number: 11853667Abstract: A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.Type: GrantFiled: July 26, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kenan Yu, Qingwen Deng
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Patent number: 11537773Abstract: A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.Type: GrantFiled: March 9, 2021Date of Patent: December 27, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kenan Yu, Qingwen Deng
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Publication number: 20220366114Abstract: A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kenan Yu, Qingwen Deng
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Publication number: 20210357561Abstract: A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.Type: ApplicationFiled: March 9, 2021Publication date: November 18, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kenan Yu, Qingwen Deng
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Patent number: 11003829Abstract: A cell library stores a plurality of standard layout cells. A functional integrated circuit design is received, and a plurality of the standard layout cells are selected from the cell library based on the received functional integrated circuit design. A first standard layout cell from the cell library that is selected based on the received functional integrated circuit design includes a buffer circuit having an input terminal, an output terminal, a first voltage terminal and a second voltage terminal, and an antenna protection circuit connected between the input terminal and the second voltage terminal.Type: GrantFiled: August 10, 2018Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kenan Yu, James Deng
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Publication number: 20200050731Abstract: A cell library stores a plurality of standard layout cells. A functional integrated circuit design is received, and a plurality of the standard layout cells are selected from the cell library based on the received functional integrated circuit design. A first standard layout cell from the cell library that is selected based on the received functional integrated circuit design includes a buffer circuit having an input terminal, an output terminal, a first voltage terminal and a second voltage terminal, and an antenna protection circuit connected between the input terminal and the second voltage terminal.Type: ApplicationFiled: August 10, 2018Publication date: February 13, 2020Inventors: Kenan Yu, James Deng
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Patent number: 7994543Abstract: A filler cell for use in fabricating an integrated circuit. The filler cell couples a power supply rail of an adjacent logic cell to a power supply rail of another adjacent logic cell. The filler cell also has a diode to bleed charge accumulated on the power rails of the adjacent logic cells to the substrate. The diode is reverse biased during normal integrated circuit operation. A method for fabricating an integrated circuit with a power grid. At least one filler cell is placed on the integrated circuit to bleed away charge accumulated on the power grid during the fabrication of the integrated circuit. The filler cell is connected to a supply rail of an adjacent logic cell.Type: GrantFiled: July 26, 2007Date of Patent: August 9, 2011Assignee: Oracle America, Inc.Inventors: Yi Wu, Kenan Yu
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Patent number: 7577933Abstract: A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design information includes a floorplan that sets forth an arrangement of blocks in the integrated circuit and timing information for interconnections between the blocks. Based on the timing information, routing information is determined for the interconnections between the blocks. The routing information includes physical routes and physical pin placements for the interconnections.Type: GrantFiled: November 17, 2006Date of Patent: August 18, 2009Assignee: Sun Microsystems, Inc.Inventors: Yi Wu, Kenan Yu, James G. Ballard
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Publication number: 20090026502Abstract: A filler cell for use in fabricating an integrated circuit. The filler cell couples a power supply rail of an adjacent logic cell to a power supply rail of another adjacent logic cell. The filler cell also has a diode to bleed charge accumulated on the power rails of the adjacent logic cells to the substrate. The diode is reverse biased during normal integrated circuit operation. A method for fabricating an integrated circuit with a power grid. At least one filler cell is placed on the integrated circuit to bleed away charge accumulated on the power grid during the fabrication of the integrated circuit. The filler cell is connected to a supply rail of an adjacent logic cell.Type: ApplicationFiled: July 26, 2007Publication date: January 29, 2009Applicant: Sun Microsystems, Inc.Inventors: Yi Wu, Kenan Yu