Abstract: A data storage system wherein end-user data is transferred between a host computer and a bank of disk drives through an interface. The interface includes a memory and a directors interconnected through an interface state data bus and end-user data busses. At least one front-end one of the directors is in communication with the host computer and at least one rear-end one of the directors is in communication with the bank of disk drives. The interface state data bus section is in communication with: both the at least one front-end one and the at least one rear-end one of the directors; and to the memory. Each one of the end-user data buses has a first end coupled to a corresponding one of the directors and a second end coupled to the memory. The directors control the end-user data transfer between the host computer and the bank of disk drives through the memory in response to interface state data generated by the directors as such end-user data passes through the end-user data busses.

Abstract: A data storage system wherein end-user data is transferred between a host computer and a bank of disk drives through an interface. The interface includes a memory and a plurality of directors interconnected through an interface state data bus and a plurality of end-user data busses. At least one front-end one of the directors is in communication with the host computer and at least one rear-end one of the directors is in communication with the bank of disk drives. The interface state data bus section is in communication with: both the at least one front-end one and the at least one rear-end one of the directors; and to the memory. Each one of the plurality of end-user data buses has a first end coupled to a corresponding one of the plurality of directors and a second end coupled to the memory.

Abstract: A data storage system wherein end-user data is transferred between a host computer and a bank of disk drives through an interface. The interface includes a memory and a plurality of directors interconnected through an interface state data bus and a plurality of end-user data busses. At least one front-end one of the directors is in communication with the host computer and at least one rear-end one of the directors is in communication with the bank of disk drives. The interface state data bus section is in communication with: both the at least one front-end one and the at least one rear-end one of the directors; and to the memory. Each one of the plurality of end-user data buses has a first end coupled to a corresponding one of the plurality of directors and a second end coupled to the memory.

Abstract: A plurality of state machines arranged into three functional units, an Upper Machine, Middle Machine and a Lower Machine facilitate movement of user data between a buffer memory and a Global Memory (GM) in a data transfer interface. The Middle Machine controls all data movement to and from the GM. Although not directly in the data path, it is responsible for coordinating control between elements that comprise data transfer channels. The Middle Machine is interconnected to and provides control and coordination between the Upper and Lower sides of the buffer memory. The Lower Machine connects to a data assembly mechanism of each pipe. The Upper Machine connects to the backplane, which in turn connects to Global Memory. The actual data transfers between the buffer memory and GM are controlled by the Upper Machine, and transfers between the buffer memory and the data assembly mechanism are controlled by the Lower Machine.

Abstract: A data storage system wherein end-user data is transferred between a host computer and a bank of disk drives through an interface. The interface includes a memory and a plurality of directors interconnected through an interface state data bus and a plurality of end-user data busses. At least one front-end one of the directors is in communication with the host computer and at least one rear-end one of the directors is in communication with the bank of disk drives. The interface state data bus section is in communication with: both the at least one front-end one and the at least one rear-end one of the directors; and to the memory. Each one of the plurality of end-user data buses has a first end coupled to a corresponding one of the plurality of directors and a second end coupled to the memory.

Abstract: An assembler/disassembler mechanism in a data transfer pipeline receives data from FIFOs on a write operation to a memory, and transfers data to FIFOs on a read operation from memory. An enhanced parity mechanism is implemented in the assembler/disassembler to generate a pseudo-random number for each data byte. Enhanced parity generated in another pipeline component and accompanying data transferred from the FIFO (on a write to memory) is exclusive-ORed with LFSR data generated by enhanced parity circuitry in the assembler/disassembler. Integral registers provide a pathway for a respective line processor to access the data string, and allow the processor to access the memory. A counter mechanism counts/controls the amount of data read into and out of the FIFOS. Setting the amount of data to be transferred in and out of the FIFOs, allows data transfer to effectively run independent of the line processor.

Abstract: A data storage system wherein end-user data is transferred between a host computer and a bank of disk drives through an interface. The interface includes a memory and a plurality of directors interconnected through an interface state data bus and a plurality of end-user data busses. At least one front-end one of the directors is in communication with the host computer and at least one rear-end one of the directors is in communication with the bank of disk drives. The interface state data bus section is in communication with: both the at least one front-end one and the at least one rear-end one of the directors; and to the memory. Each one of the plurality of end-user data buses has a first end coupled to a corresponding one of the plurality of directors and a second end coupled to the memory.

Abstract: An assembler/disassembler mechanism in a data transfer pipeline receives data from FIFOs on a write operation to a memory, and transfers data to FIFOs on a read operation from memory. An enhanced parity mechanism is implemented in the assembler/disassembler to generate a pseudo-random number for each data byte. Enhanced parity generated in another pipeline component and accompanying data transferred from the FIFO (on a write to memory) is exclusive-ORed with LFSR data generated by enhanced parity circuitry in the assembler/disassembler. Integral registers provide a pathway for a respective line processor to access the data string, and allow the processor to access the memory. A counter mechanism counts/controls the amount of data read into and out of the FIFOs. Setting the amount of data to be transferred in and out of the FIFOs, allows data transfer to effectively run independent of the line processor.

Abstract: An interface architecture includes a plurality of pipelines each controlled by a respective line processor. An onboard ESCON protocol conversion device distinguishes customer data to be stored on a disk or read from disk versus header information. Transmit and receive frame dual port rams store transmitted frame and received frame information, stripping frame/header information from user data. Data to be stored in Global Memory is stored temporarily in FIFOs. An assembler/disassembler in each pipeline receives data from FIFOs (on a write), and transfers data to FIFOs (on a read). A buffer dual port ram (DPR) is configured to receive data for buffering read operations from and write operations to the GM. Data transfers between the assembler/disassembler and the buffer DPR pass through Error Detection And Correction circuitry (EDAC). A plurality of state machines arranged as an Upper Machine, Middle Machine and Lower Machine facilitate movement of user data between DPR and Global Memory (GM).

Abstract: A plurality of state machines arranged into three functional units, an Upper Machine, Middle Machine and a Lower Machine facilitate movement of user data between a buffer memory and a Global Memory (GM) in a data transfer interface. The Middle Machine controls all data movement to and from the GM. Although not directly in the data path, it is responsible for coordinating control between elements that comprise data transfer channels. The Middle Machine is interconnected to and provides control and coordination between the Upper and Lower sides of the buffer memory. The Lower Machine connects to a data assembly mechanism of each pipe. The Upper Machine connects to the backplane, which in turn connects to Global Memory. The actual data transfers between the buffer memory and GM are controlled by the Upper Machine, and transfers between the buffer memory and the data assembly mechanism are controlled by the Lower Machine.