Abstract: A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (Vss) and/or Vcc for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n+-type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n+ source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.

Abstract: According to one embodiment, a nonvolatile circuit (100) can include a volatile circuit portion (102) and a nonvolatile circuit portion (104). A vole portion (102) may have a first data node (114) and a second data node (116). A nonvolatile circuit portion (104) may include a nonvolatile device (128) that is connected to a first data node (114) by a recall device (124) and connected to a second data node (116) by store device (126). A recall device (124) may be enabled to recall the volatile circuit portion (102) to a particular state. A store device (126) may be enabled to program a nonvolatile device (128). Store and recall devices (126 and 124) can enable a recall operation to follow a store operation that does not invert data at first and second data nodes (114 and 116). A control device (122) can be included that enables margin testing of a nonvolatile device (128).

Abstract: A circuit comprising a positive switch and a steering network. The positive switch may be configured to present a first and a second switch signal in response to a first select signal. The steering network may be configured to present a high voltage output that may transition between a very high positive and a very low negative voltage, where the transition may respond to a high positive voltage input, a low negative voltage input, a first and second switch signal, and a second select signal.

Abstract: A high voltage switch for use in an EEPROM/FLASH memory that may be implemented using a twin-well process (e.g., using only P-channel transistors). The circuit comprises a positive switch configured to present a first and a second switch signal in response to (i) one or more select signals and (ii) an address signal and a second switch configured to present a programing voltage in response to (i) the select signals, (ii) the first and second switch signals and (iii) a high voltage source. A high voltage positive and negative pump may provide the high voltage source.

Abstract: A method and apparatus comprising a first circuit configured to generate a first output in response to a first input, a second circuit configured to present a second output in response to a second input, and a third circuit configured to generate a first voltage signal and a second voltage signal in response to the first output and said second output. The first voltage signal may be above the positive supply and the second voltage signal may be below the negative supply.