Patents by Inventor Keng-Chu Lin

Keng-Chu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220139773
    Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.
    Type: Application
    Filed: January 13, 2022
    Publication date: May 5, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li WANG, Shuen-Shin LIANG, Yu-Yun PENG, Fang-Wei LEE, Chia-Hung CHU, Mrunal Abhijith KHADERBAD, Keng-Chu LIN
  • Publication number: 20220130755
    Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 28, 2022
    Inventors: SHUEN-SHIN LIANG, KEN-YU CHANG, HUNG-YI HUANG, CHIEN CHANG, CHI-HUNG CHUANG, KAI-YI CHU, CHUN-I TSAI, CHUN-HSIEN HUANG, CHIH-WEI CHANG, HSU-KAI CHANG, CHIA-HUNG CHU, KENG-CHU LIN, SUNG-LI WANG
  • Publication number: 20220123152
    Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 21, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Khaderbad Mrunal Abhijith, Keng-Chu LIN, Yu-Yun PENG
  • Publication number: 20220108919
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 7, 2022
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Patent number: 11296187
    Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
  • Patent number: 11257753
    Abstract: The present disclosure provides an interconnect structure, including a substrate having a conductive region adjacent to a gate region, a contact over the conductive region, a first interlayer dielectric layer (ILD) surrounding the contact, a via over the contact, a first densified dielectric layer surrounding the via, wherein the densified dielectric layer has a first density, and a second ILD layer over the first ILD layer and surrounding the via, wherein the second ILD layer has a second density, the first density is greater than a second density.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Khaderbad Mrunal Abhijith, Yu-Yun Peng, Fu-Ting Yen, Chen-Han Wang, Tsu-Hsiu Perng, Keng-Chu Lin
  • Publication number: 20220020644
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure.
    Type: Application
    Filed: January 7, 2021
    Publication date: January 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu LIN, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11227794
    Abstract: A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
  • Patent number: 11217524
    Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shuen-Shin Liang, Ken-Yu Chang, Hung-Yi Huang, Chien Chang, Chi-Hung Chuang, Kai-Yi Chu, Chun-I Tsai, Chun-Hsien Huang, Chih-Wei Chang, Hsu-Kai Chang, Chia-Hung Chu, Keng-Chu Lin, Sung-Li Wang
  • Publication number: 20210407856
    Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tetsuji Ueno, Ting-Ting Chen
  • Publication number: 20210399099
    Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least on channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.
    Type: Application
    Filed: January 4, 2021
    Publication date: December 23, 2021
    Inventors: Chia-Hung Chu, Sung-Li Wang, Shuen-Shin Liang, Hsu-Kai Chang, Ding-Kang Shih, Tsungyu Hung, Pang-Yen Tsai, Keng-Chu Lin
  • Patent number: 11205742
    Abstract: A luminescent material, a light emitting device, and a display device are disclosed. The luminescent material includes particles and a phosphor. The particles include quantum dots and have an average diameter of 0.06 ?m to 30 ?m.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: December 21, 2021
    Assignee: CHIMEI CORPORATION
    Inventors: Yuan-Ren Juang, Szu-Chun Yu, Keng-Chu Lin, Wei-Ta Chen, Yao-Tsung Chuang, Jen-Shrong Uen
  • Publication number: 20210391252
    Abstract: The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: SHUEN-SHIN LIANG, KEN-YU CHANG, HUNG-YI HUANG, CHIEN CHANG, CHI-HUNG CHUANG, KAI-YI CHU, CHUN-I TSAI, CHUN-HSIEN HUANG, CHIH-WEI CHANG, HSU-KAI CHANG, CHIA-HUNG CHU, KENG-CHU LIN, SUNG-LI WANG
  • Publication number: 20210375667
    Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.
    Type: Application
    Filed: July 12, 2021
    Publication date: December 2, 2021
    Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
  • Publication number: 20210376103
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
  • Publication number: 20210359125
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple channel structures suspended over a semiconductor substrate. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the channel structures. The semiconductor device structure further includes a gate stack wrapping around the channel structures. In addition, the semiconductor device structure includes a conductive contact wrapping around terminals of the epitaxial structures.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Pang-Yen TSAI, Keng-Chu LIN, Sung-Li WANG, Pinyen LIN
  • Patent number: 11171263
    Abstract: The present disclosure provides a quantum dot and a manufacturing method for the same, and a luminescent material, a light-emitting element and a display device applying the quantum dot. The quantum dot includes a nano-crystal and a ligand. The nano-crystal is at least one selected from the group consisting of a XII-XV group compound semiconductor nano-crystal, a XII-XVI group compound semiconductor nano-crystal, a XIII-XV group compound semiconductor nano-crystal and a XIII-XVI group compound semiconductor nano-crystal. The ligand is disposed on a surface of the nano-crystal. The ligand contains 15%-70% of a fatty acid compound, 1%-35% of a phosphine compound, >0%-55% of a thiol compound, and 0%-10% of another ligand substance.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 9, 2021
    Assignee: CHIMEI CORPORATION
    Inventor: Keng-Chu Lin
  • Publication number: 20210335720
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Application
    Filed: January 5, 2021
    Publication date: October 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
  • Patent number: 11158539
    Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature; etching a hole through the dielectric layer and exposing the conductive feature; depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature; depositing a second metal over the first metal; and annealing the structure including the first and the second metals.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Hung-Yi Huang, Yu-Yun Peng, Mrunal A. Khaderbad, Chia-Hung Chu, Shuen-Shin Liang, Keng-Chu Lin
  • Publication number: 20210305372
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.
    Type: Application
    Filed: July 23, 2020
    Publication date: September 30, 2021
    Inventors: Mrunal Abhijith Khaderbad, Dhanyakumar Mahaveer Sathaiya, Keng-Chu Lin, Tzer-Min Shen