Patents by Inventor Keng-Jen Lin
Keng-Jen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990547Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.Type: GrantFiled: September 27, 2020Date of Patent: May 21, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
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Publication number: 20220069127Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.Type: ApplicationFiled: September 27, 2020Publication date: March 3, 2022Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
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Patent number: 10460925Abstract: A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.Type: GrantFiled: June 30, 2017Date of Patent: October 29, 2019Assignee: United Microelectronics Corp.Inventors: Hsu Ting, Kuang-Hsiu Chen, Chun-Wei Yu, Keng-Jen Lin, Yu-Ren Wang
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Patent number: 10366991Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.Type: GrantFiled: January 25, 2018Date of Patent: July 30, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsu Ting, Yu-Ying Lin, Yen-Hsing Chen, Chun-Jen Chen, Chun-Wei Yu, Keng-Jen Lin, Yu-Ren Wang
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Publication number: 20190221562Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.Type: ApplicationFiled: January 25, 2018Publication date: July 18, 2019Inventors: Hsu Ting, Yu-Ying Lin, Yen-Hsing Chen, Chun-Jen Chen, Chun-Wei Yu, Keng-Jen Lin, Yu-Ren Wang
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Patent number: 10347640Abstract: The invention provides a manufacturing method of a semiconductor device. First, a substrate is provided. A first recess and a second recess are formed in the substrate, a width of the first recess is smaller than a width of the second recess. Then, a first spin-on dielectric (SOD) layer is formed to fill the first recess and partially fill in the second recess, and then a first processing step is performed to transfer the first SOD layer into a first silicon oxide layer, a silicon nitride layer is subsequently formed on the first silicon oxide layer in the second recess, and then a second spin-on dielectric (SOD) layer is formed on the silicon nitride layer in the second recess, and a second processing step is performed to transfer the second SOD layer into a second silicon oxide layer.Type: GrantFiled: August 1, 2018Date of Patent: July 9, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Ya-Ying Tsai, Keng-Jen Lin
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Publication number: 20190006172Abstract: A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Applicant: United Microelectronics Corp.Inventors: Hsu Ting, Kuang-Hsiu Chen, Chun-Wei Yu, Keng-Jen Lin, Yu-Ren Wang
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Patent number: 10043888Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure includes a substrate and a plurality of fins formed on the substrate. Then, a first polysilicon layer is formed on the substrate. The first polysilicon layer covers at least portions of the fins. An amorphous silicon layer is formed on the first polysilicon layer.Type: GrantFiled: December 27, 2016Date of Patent: August 7, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Hui Lin, Keng-Jen Lin, Yu-Ren Wang
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Publication number: 20180182862Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure includes a substrate and a plurality of fins formed on the substrate. Then, a first polysilicon layer is formed on the substrate. The first polysilicon layer covers at least portions of the fins. An amorphous silicon layer is formed on the first polysilicon layer.Type: ApplicationFiled: December 27, 2016Publication date: June 28, 2018Inventors: Yi-Hui Lin, Keng-Jen Lin, Yu-Ren Wang
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Patent number: 9847247Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.Type: GrantFiled: May 9, 2017Date of Patent: December 19, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
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Patent number: 9793174Abstract: A fin field effect transistor (FinFET) on a silicon-on-insulator and method of forming the same are provided in the present invention. The FinFET includes first fin structure, second fin structure and an insulating layer. The first fin structure and the second fin structure are disposed on a substrate. The insulating layer covers the first fin structure and the second fin structure and exposes a first portion of the first fin structure and a second portion of the second fin structure. The first fin structure has a first height and the second fin structure has a second height different from the first height, and a top surface of the first fin structure and a top surface of the second fin structure are at different levels.Type: GrantFiled: September 20, 2016Date of Patent: October 17, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ping-Wei Huang, Yu-Ren Wang, Keng-Jen Lin, Shu-Ming Yeh
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Publication number: 20170243780Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.Type: ApplicationFiled: May 9, 2017Publication date: August 24, 2017Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
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Patent number: 9685319Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.Type: GrantFiled: July 22, 2015Date of Patent: June 20, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
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Patent number: 9570578Abstract: A gate forming process includes the following steps. A gate dielectric layer is formed on a substrate. A barrier layer is formed on the gate dielectric layer. A silicon seed layer and a silicon layer are sequentially and directly formed on the barrier layer, wherein the silicon seed layer and the silicon layer are formed by different precursors.Type: GrantFiled: February 11, 2015Date of Patent: February 14, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Keng-Jen Lin, Chien-Liang Lin, Yu-Ren Wang, Neng-Hui Yang
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Patent number: 9543408Abstract: A method of forming a patterned hark mask layer includes the following steps. A semiconductor substrate is provided. An amorphous silicon layer is formed on the semiconductor substrate. An implantation process is performed on the amorphous silicon layer. An annealing treatment is performed on the amorphous silicon layer after the implantation process. A patterned hard mask layer is formed on the amorphous silicon layer after the annealing treatment.Type: GrantFiled: August 26, 2015Date of Patent: January 10, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Hui Lin, Keng-Jen Lin, Chun-Yao Yang, Yu-Ren Wang
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Publication number: 20160365245Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.Type: ApplicationFiled: July 22, 2015Publication date: December 15, 2016Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
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Patent number: 9418853Abstract: The present invention provides a method for forming a stacked layer structure, including: first, a recess is provided, next, an oxide layer is formed in the recess, where the oxide layer has a thickness T1, a high-k layer is formed on the oxide layer, a barrier layer is formed on the high-k layer, a silicon layer is then formed on the barrier layer, afterwards, an annealing process is performed on the silicon layer, so as to form an oxygen-containing layer between the silicon layer and the barrier layer, where the oxide layer has a thickness T2 after the annealing process is performed, and satisfies the relationship: (T2?T1)/T1?0.05, and the silicon layer and the oxygen-containing layer are removed.Type: GrantFiled: April 21, 2015Date of Patent: August 16, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shao-Wei Wang, Keng-Jen Lin, Yu-Tung Hsiao, Shu-Ming Yeh
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Publication number: 20160233092Abstract: A gate forming process includes the following steps. A gate dielectric layer is formed on a substrate. A barrier layer is formed on the gate dielectric layer. A silicon seed layer and a silicon layer are sequentially and directly formed on the barrier layer, wherein the silicon seed layer and the silicon layer are formed by different precursors.Type: ApplicationFiled: February 11, 2015Publication date: August 11, 2016Inventors: Keng-Jen Lin, Chien-Liang Lin, Yu-Ren Wang, Neng-Hui Yang
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Patent number: 9356125Abstract: A manufacturing method of a semiconductor structure includes the following steps. A high-k dielectric layer is formed on a semiconductor substrate, and a barrier layer is formed on the high-k dielectric layer. An oxygen annealing treatment is performed after the step of forming the barrier layer; and a capping layer is formed on the barrier layer after the oxygen annealing treatment.Type: GrantFiled: July 28, 2015Date of Patent: May 31, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Tung Hsiao, Keng-Jen Lin, Yu-Ren Wang
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Patent number: 9130014Abstract: A method for fabricating shallow trench isolation structure is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a trench in the substrate; (c) forming a silicon layer in the trench; and (d) performing an oxidation process to partially transform a surface of the silicon layer into an oxide layer.Type: GrantFiled: November 21, 2013Date of Patent: September 8, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Keng-Jen Lin, Yu-Ren Wang, Chien-Liang Lin, Tsuo-Wen Lu, Wei-Jen Chen, Chih-Chung Chen