Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

Abstract: A device and method for detecting crystal quality of a low temperature poly-silicon (LTPS) backplane are provided, the method including: projecting narrowband light to the LTPS backplane; performing image capturing of each position on a surface of the LTPS backplane at a first angle in a first axial direction to obtain a first diffraction image, the first angle being an angle of maximum diffraction light intensity in the first axial direction; performing another image capturing of each position on the surface of the LTPS backplane at a second angle in a second axial direction to obtain a second diffraction image, the second angle being an angle of maximum diffraction light intensity in the second axial direction; and determining the crystal quality of the LTPS backplane based on a diffraction light intensity distribution obtained from the first and second diffraction images.

Abstract: A method for labeling connected components and a computer system using the method are provided. With the method, during a process of scanning an image for the first time, each object pixel in the image is assigned a temporary label, and a relationship between each temporary label and a representative label is established after the completion of the process of scanning the image for the first time. Thereafter, the temporary label of each object pixel is replaced by the corresponding representative label during a process of scanning the image for the second time. As a result, the labeling of the connected components can be accomplished by only scanning the image twice such that the efficiency of labeling the connected components can be significantly improved.

Abstract: The present invention provides a lead-free brass alloy, including 0.3 to 0.8 wt % of aluminum, 0.01 to 0.4 wt % of bismuth, 0.05 to 1.5 wt % of iron and more than 96 wt % of copper and zinc, wherein the copper is present in an amount ranging from 58 to 75 wt %. The brass alloy of the present invention meets the standard of the environmental regulation, wherein the lead content is less than 0.25 wt % based on the weight of the alloy. Further, the brass alloy of the present invention has 0.05 to 1.5 wt % of iron and less than 0.4% of bismuth, so as to lower production cost, eliminate cracks and increase production yield.

Abstract: A method for labeling connected components and a computer system using the method are provided. With the method, during a process of scanning an image for the first time, each object pixel in the image is assigned a temporary label, and a relationship between each temporary label and a representative label is established after the completion of the process of scanning the image for the first time. Thereafter, the temporary label of each object pixel is replaced by the corresponding representative label during a process of scanning the image for the second time. As a result, the labeling of the connected components can be accomplished by only scanning the image twice such that the efficiency of labeling the connected components can be significantly improved.