Patents by Inventor Keng-Ping Lin
Keng-Ping Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11610897Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.Type: GrantFiled: April 8, 2021Date of Patent: March 21, 2023Assignee: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Tetsuharu Kurokawa, Tzu-Ming Ou Yang, Shu-Ming Li
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Publication number: 20230049425Abstract: A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.Type: ApplicationFiled: October 26, 2022Publication date: February 16, 2023Applicant: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Shu-Ming Li, Tzu-Ming Ou Yang
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Patent number: 11527537Abstract: A memory structure including a substrate, a bit line structure, a contact structure, a stop layer, and a capacitor structure is provided. The substrate includes a memory array region. The bit line structure is located in the memory array region and located on the substrate. The contact structure is located in the memory array region and located on the substrate on one side of the bit line structure. The stop layer is located in the memory array region and located above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. A bottom surface of the capacitor structure is lower than a bottom surface of the stop layer.Type: GrantFiled: May 3, 2021Date of Patent: December 13, 2022Assignee: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Shu-Ming Li, Tzu-Ming Ou Yang
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Publication number: 20220352172Abstract: A memory structure including a substrate, a bit line structure, a contact structure, a stop layer, and a capacitor structure is provided. The substrate includes a memory array region. The bit line structure is located in the memory array region and located on the substrate. The contact structure is located in the memory array region and located on the substrate on one side of the bit line structure. The stop layer is located in the memory array region and located above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. A bottom surface of the capacitor structure is lower than a bottom surface of the stop layer.Type: ApplicationFiled: May 3, 2021Publication date: November 3, 2022Applicant: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Shu-Ming Li, Tzu-Ming Ou Yang
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Patent number: 11289493Abstract: A patterning method includes sequentially forming a target layer, a first layer, a second layer, a third layer, and a first mask pattern. A first spacer is formed on a sidewall of the first mask layer. The first mask pattern is removed to form a plurality of peripheral openings surrounding a central opening in the first spacer. A rounding process is performed to round the peripheral openings and form a second mask pattern. A portion of the second layer is removed by using the second mask pattern as a mask, so as to form a third mask pattern. A second spacer is formed in the third mask pattern. The third mask pattern is removed. Portions of the first layer and the target layer are removed by using the second spacer as a mask.Type: GrantFiled: October 31, 2019Date of Patent: March 29, 2022Assignee: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Tzu-Ming Ou Yang
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Publication number: 20210225850Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.Type: ApplicationFiled: April 8, 2021Publication date: July 22, 2021Applicant: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Tetsuharu Kurokawa, Tzu-Ming Ou Yang, Shu-Ming Li
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Patent number: 11011525Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.Type: GrantFiled: August 29, 2019Date of Patent: May 18, 2021Assignee: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Tetsuharu Kurokawa, Tzu-Ming Ou Yang, Shu-Ming Li
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Publication number: 20210134810Abstract: A patterning method includes sequentially forming a target layer, a first layer, a second layer, a third layer, and a first mask pattern. A first spacer is formed on a sidewall of the first mask layer. The first mask pattern is removed to form a plurality of peripheral openings surrounding a central opening in the first spacer. A rounding process is performed to round the peripheral openings and form a second mask pattern. A portion of the second layer is removed by using the second mask pattern as a mask, so as to form a third mask pattern. A second spacer is formed in the third mask pattern. The third mask pattern is removed. Portions of the first layer and the target layer are removed by using the second spacer as a mask.Type: ApplicationFiled: October 31, 2019Publication date: May 6, 2021Applicant: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Tzu-Ming Ou Yang
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Patent number: 10985262Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a plurality of gate structures, a plurality of dielectric structures, and spacers. The plurality of gate structures is disposed on the substrate. The plurality of dielectric structures is respectively disposed between the gate structures and the substrate, wherein a top width of the dielectric structure is less than the bottom width of the dielectric structure. The spacers are disposed on the sidewalls of the gate structures and cover the sidewalls of the dielectric structures.Type: GrantFiled: October 24, 2018Date of Patent: April 20, 2021Assignee: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Tzu-Ming Ou Yang, Shu-Ming Li, Tetsuharu Kurokawa
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Publication number: 20200219889Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.Type: ApplicationFiled: August 29, 2019Publication date: July 9, 2020Applicant: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Tetsuharu Kurokawa, Tzu-Ming Ou Yang, Shu-Ming Li
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Publication number: 20190140069Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a plurality of gate structures, a plurality of dielectric structures, and spacers. The plurality of gate structures is disposed on the substrate. The plurality of dielectric structures is respectively disposed between the gate structures and the substrate, wherein a top width of the dielectric structure is less than the bottom width of the dielectric structure. The spacers are disposed on the sidewalls of the gate structures and cover the sidewalls of the dielectric structures.Type: ApplicationFiled: October 24, 2018Publication date: May 9, 2019Applicant: Winbond Electronics Corp.Inventors: Keng-Ping Lin, Tzu-Ming Ou Yang, Shu-Ming Li, Tetsuharu Kurokawa