Abstract: In some embodiments a functional PCI Express port includes first buffers and an idle PCI Express port includes second buffers. One or more of the second buffers are accessed by the functional PCI Express port. Other embodiments are described and claimed.

Abstract: In some embodiments a functional PCI Express port includes first buffers and an idle PCI Express port includes second buffers. One or more of the second buffers are accessed by the functional PCI Express port. Other embodiments are described and claimed.

Abstract: In some embodiments a functional PCI Express port includes first buffers and an idle PCI Express port includes second buffers. One or more of the second buffers are accessed by the functional PCI Express port. Other embodiments are described and claimed.

Abstract: Methods and apparatus for achieving high bus bandwidth transfer using a split data bus. A data bus is split into multiple segments whose access is, individually controlled by an arbitration control unit in a manner that supports concurrent data transfers. Thus, the split data bus is able to concurrently transfer data between multiple master-slave pairs during a given data cycle. A split address but is provided to allow concurrent access requests to be considered for grant. In one embodiment, the data bus includes a read data bus and a write data bus.

Abstract: Methods and apparatus for achieving high bus bandwidth transfer using a split data bus. A data bus is split into multiple segments whose access is, individually controlled by an arbitration control unit in a manner that supports concurrent data transfers. Thus, the split data bus is able to concurrently transfer data between multiple master-slave pairs during a given data cycle. A split address but is provided to allow concurrent access requests to be considered for grant. In one embodiment, the data bus includes a read data bus and a write data bus.