Patents by Inventor Kengo Aoya

Kengo Aoya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140626
    Abstract: An electronic device includes a package structure having opposite first and second sides, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, the first and second sides spaced along a third direction orthogonal to the first and second directions, and an opening extending into the first side along the third direction, a first semiconductor die having a first side exposed in the opening of the package structure and an opposite second side partially enclosed by the package structure, and a second semiconductor die electrically connected to the first semiconductor die, the second semiconductor die enclosed by the package structure and laterally spaced apart from the first semiconductor die.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 1, 2025
    Inventors: Masamitsu Matsuura, Daiki Komatsu, Kengo Aoya
  • Patent number: 12272626
    Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 8, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Anindya Poddar
  • Publication number: 20250112182
    Abstract: A semiconductor package includes a semiconductor wafer having a first connection pad and a second connection pad spaced apart by a semiconductor region of the semiconductor wafer. Portions of the semiconductor wafer are covered by a protective overcoat. The semiconductor package also includes a cap wafer mounted to the semiconductor wafer and overpassing the semiconductor region of the semiconductor wafer. The cap wafer extends between the first connection pad and the second connection pad of the semiconductor wafer. The semiconductor package further includes an insulation material overlaying the cap wafer. The insulation material comprising vias to the first connection pad and the second connection pad, the vias being filled with a conductive material.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Masamitsu Matsuura, Daiki Komatsu, Kengo Aoya, Ting-Ta Yen
  • Publication number: 20250087591
    Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 13, 2025
    Inventors: Woochan Kim, Masamitsu Matasuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar, Hideaki Matsunaga
  • Publication number: 20250038009
    Abstract: A semiconductor package has a relief recess in the mold compound, extending around the perimeter over the leads. The relief recess has a relief width greater than a thickness of the leads under the relief recess. Top surfaces of the leads may be exposed at the relief recess, or may be covered by the mold compound under the relief recess. In both cases, a height difference between the mold compound under the relief recess and the leads under the relief recess is less than the thickness of the leads under the relief recess. A majority of exposed side faces of the leads are characteristic of sawn surfaces, which includes leads being free of vertical striations or having burrs along bottom edges. The semiconductor package is singulated by sawing through the leads.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 30, 2025
    Inventors: Kengo Aoya, Masamitsu Matsuura, Daiki Komatsu
  • Patent number: 12154861
    Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: November 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Masamitsu Matasuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar, Hideaki Matsunaga
  • Publication number: 20240379509
    Abstract: In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Makoto SHIBUYA, Makoto YOSHINO, Kengo AOYA
  • Patent number: 12125799
    Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: October 22, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora, Anindya Poddar
  • Publication number: 20240290676
    Abstract: A microelectronic device includes one or more electronic components attached to a package substrate which has an exposed surface to provide an area for mounting a heatsink. The microelectronic device includes one or more leads that are electrically connected to the electronic component. The lead extends away from the exposed surface of the package substrate. The microelectronic device includes a shielding dielectric material that laterally surrounds the lead and extends over the lead between the lead and the exposed surface of the package substrate. An electronic system includes the microelectronic device and a circuit board electrically connected to the lead. The electronic system also includes a heatsink attached to the exposed surface of the package substrate.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 29, 2024
    Inventors: Masamitsu Matsuura, Makoto Shibuya, Daiki Komatsu, Kengo Aoya
  • Publication number: 20240258214
    Abstract: An example electronic device includes a substrate having a die pad and a semiconductor device on the die pad electrically connected to the substrate. The device also includes a mold compound over the semiconductor device to provide a packaged electronic device. The packaged electronic device has respective side edges that extend from a first end to terminate in a second end at a distal surface of the mold compound that is spaced apart from the substrate. At least one side edge of the mold compound has a respective surface that is orthogonal to the distal surface and includes a notch extending inwardly from the respective surface.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 1, 2024
    Inventors: Makoto SHIBUYA, Kengo AOYA
  • Patent number: 12046542
    Abstract: In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: July 23, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Makoto Yoshino, Kengo Aoya
  • Patent number: 12040260
    Abstract: An electronic package includes an electronic component including terminals, a plurality of surface contacts, at least some of the surface contacts being electrically coupled to the terminals within the electronic package, a mold compound covering the electronic component and partially covering the surface contacts with a bottom surface exposed from the mold compound, and a plurality of wires extending from exposed surfaces of the surface contacts, each of the wires providing a solderable surface for mounting the electronic package at a standoff on an external board.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: July 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Ayumu Kuroda, Kengo Aoya
  • Publication number: 20240213178
    Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.
    Type: Application
    Filed: March 5, 2024
    Publication date: June 27, 2024
    Inventors: Tomoko NOGUCHI, Mutsumi MASUMOTO, Kengo AOYA, Masamitsu MATSUURA
  • Publication number: 20240178164
    Abstract: An electronic device includes a semiconductor substrate having a first conductive routing structure on a first side of the semiconductor substrate, and a low aspect ratio via opening extending from the first side to an opposite second side. The electronic device includes a transparent cover over a portion of the first side and covering the patterned first conductive routing structure, as well as an insulator layer including a photo-imageable material on the second side and along a sidewall of the via opening, and a second conductive routing structure on an outer side of the insulator layer and extending through the via opening and directly contacting a portion of the first conductive routing structure.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Masamitsu Matsuura, Kengo Aoya, Daiki Komatsu, Ko Shibata
  • Patent number: 11942384
    Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar
  • Patent number: 11923320
    Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tomoko Noguchi, Mutsumi Masumoto, Kengo Aoya, Masamitsu Matsuura
  • Patent number: 11848244
    Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: December 19, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya
  • Publication number: 20230275007
    Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.
    Type: Application
    Filed: February 28, 2022
    Publication date: August 31, 2023
    Inventors: Makoto SHIBUYA, Masamitsu Matsuura, Kengo Aoya, Anindya Poddar
  • Publication number: 20230198422
    Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.
    Type: Application
    Filed: February 14, 2023
    Publication date: June 22, 2023
    Inventors: Woochan Kim, Vivek Kishorechand Arora, Makoto Shibuya, Kengo Aoya
  • Publication number: 20230137762
    Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar