Patents by Inventor Kengo Aoya

Kengo Aoya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178164
    Abstract: An electronic device includes a semiconductor substrate having a first conductive routing structure on a first side of the semiconductor substrate, and a low aspect ratio via opening extending from the first side to an opposite second side. The electronic device includes a transparent cover over a portion of the first side and covering the patterned first conductive routing structure, as well as an insulator layer including a photo-imageable material on the second side and along a sidewall of the via opening, and a second conductive routing structure on an outer side of the insulator layer and extending through the via opening and directly contacting a portion of the first conductive routing structure.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Masamitsu Matsuura, Kengo Aoya, Daiki Komatsu, Ko Shibata
  • Patent number: 11942384
    Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar
  • Patent number: 11923320
    Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tomoko Noguchi, Mutsumi Masumoto, Kengo Aoya, Masamitsu Matsuura
  • Patent number: 11848244
    Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: December 19, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya
  • Publication number: 20230275007
    Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.
    Type: Application
    Filed: February 28, 2022
    Publication date: August 31, 2023
    Inventors: Makoto SHIBUYA, Masamitsu Matsuura, Kengo Aoya, Anindya Poddar
  • Publication number: 20230198422
    Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.
    Type: Application
    Filed: February 14, 2023
    Publication date: June 22, 2023
    Inventors: Woochan Kim, Vivek Kishorechand Arora, Makoto Shibuya, Kengo Aoya
  • Publication number: 20230137762
    Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar
  • Publication number: 20230095630
    Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Inventors: Makoto SHIBUYA, Masamitsu MATSUURA, Kengo AOYA
  • Patent number: 11601065
    Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 7, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Vivek Kishorechand Arora, Makoto Shibuya, Kengo Aoya
  • Publication number: 20230060830
    Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Woochan Kim, Vivek Kishorechand Arora, Makoto Shibuya, Kengo Aoya
  • Publication number: 20220352055
    Abstract: In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 3, 2022
    Inventors: Makoto SHIBUYA, Makoto YOSHINO, Kengo AOYA
  • Patent number: 11410875
    Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 9, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hau Thanh Nguyen, Woochan Kim, Yi Yan, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Masamitsu Matsuura, Kengo Aoya, Mutsumi Masumoto
  • Patent number: 11387179
    Abstract: An integrated circuit (IC) package includes a substrate having a first region and a second region. The substrate includes a conductive path between the first region and the second region. The IC package also includes a lead frame having a first member and a second member that are spaced apart. The IC package further includes a half-bridge power module. The half-bridge power module includes a capacitor having a first node coupled to the first member of the lead frame and a second node coupled to the second member of the lead frame. The half-bridge power module also includes a high side die having a high side field effect transistor (FET) embedded therein and a low side die having a low side FET embedded therein. A source of the high side FET is coupled to a drain of the low side FET through the conductive path of the substrate.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: July 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Kengo Aoya, Woochan Kim, Vivek Kishorechand Arora
  • Publication number: 20220208660
    Abstract: An electronic package includes an electronic component including terminals, a plurality of surface contacts, at least some of the surface contacts being electrically coupled to the terminals within the electronic package, a mold compound covering the electronic component and partially covering the surface contacts with a bottom surface exposed from the mold compound, and a plurality of wires extending from exposed surfaces of the surface contacts, each of the wires providing a solderable surface for mounting the electronic package at a standoff on an external board.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Inventors: Makoto Shibuya, Ayumu Kuroda, Kengo Aoya
  • Publication number: 20220208689
    Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Inventors: Tomoko NOGUCHI, Mutsumi MASUMOTO, Kengo AOYA, Masamitsu MATSUURA
  • Publication number: 20220108955
    Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.
    Type: Application
    Filed: November 2, 2021
    Publication date: April 7, 2022
    Inventors: Woochan Kim, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora, Anindya Poddar
  • Publication number: 20220068556
    Abstract: In examples, a transformer device comprises a first magnetic member; a second magnetic member; and a substrate layer between the first and second magnetic members. The substrate layer comprises a transformer coil. The transformer device includes a third magnetic member inside the substrate layer. The transformer coil encircles the third magnetic member. The third magnetic member physically separates from the first and second magnetic members.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 3, 2022
    Inventors: Yi YAN, Kengo AOYA, Tomoko NOGUCHI, Tatsuhiro SHIMIZU
  • Patent number: 11183441
    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
  • Patent number: 11183460
    Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: November 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Woochan Kim, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora, Anindya Poddar
  • Patent number: 11158595
    Abstract: An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: October 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar