Patents by Inventor Kengo Kotoo
Kengo Kotoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230268368Abstract: Electrical connection between mutually facing electrodes is provided. A solid-state imaging device includes: a first semiconductor base; a second semiconductor base bonded to the first semiconductor base; and a conductive polymer, the first semiconductor base including a first semiconductor layer in which a photoelectric conversion unit is provided, a first multilayer wiring layer stacked on the first semiconductor layer, and a first metal pad formed on a surface of the first multilayer wiring layer on a side opposite to the first semiconductor layer, the second semiconductor base including a second semiconductor layer in which an active element is provided, a second multilayer wiring layer stacked on the second semiconductor layer, and a second metal pad on a surface of the second multilayer wiring layer on a side opposite to the second semiconductor layer, the conductive polymer electrically connecting the first metal pad and to the second metal pad.Type: ApplicationFiled: August 16, 2021Publication date: August 24, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Kengo KOTOO
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Publication number: 20210320141Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Applicant: SONY GROUP CORPORATIONInventors: Kengo KOTOO, Kaoru KOIKE
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Patent number: 11069735Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.Type: GrantFiled: June 30, 2020Date of Patent: July 20, 2021Assignee: SONY CORPORATIONInventors: Kengo Kotoo, Kaoru Koike
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Publication number: 20200335543Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.Type: ApplicationFiled: June 30, 2020Publication date: October 22, 2020Applicant: Sony CorporationInventors: Kengo KOTOO, Kaoru KOIKE
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Patent number: 10720462Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.Type: GrantFiled: June 12, 2019Date of Patent: July 21, 2020Assignee: Sony CorporationInventors: Kengo Kotoo, Kaoru Koike
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Publication number: 20190296073Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.Type: ApplicationFiled: June 12, 2019Publication date: September 26, 2019Applicant: Sony CorporationInventors: Kengo KOTOO, Kaoru KOIKE
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Patent number: 10355039Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.Type: GrantFiled: April 26, 2016Date of Patent: July 16, 2019Assignee: Sony CorporationInventors: Kengo Kotoo, Kaoru Koike
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Publication number: 20180138223Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.Type: ApplicationFiled: April 26, 2016Publication date: May 17, 2018Inventors: Kengo KOTOO, Kaoru KOIKE
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Patent number: 9419040Abstract: There is provided a solid state image pickup apparatus including a first semiconductor substrate and a second semiconductor substrate which are bonded to each other, and a buried portion formed in a peripheral portion of the apparatus with a depth of a bonded surface of the first semiconductor substrate and the second semiconductor substrate in such a manner that the bonded surface of the first semiconductor substrate and the second semiconductor substrate is not exposed.Type: GrantFiled: January 23, 2015Date of Patent: August 16, 2016Assignee: SONY CORPORATIONInventors: Kenta Nojima, Kengo Kotoo, Hirotaka Yoshioka, Kenta Ikeda
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Publication number: 20150214263Abstract: There is provided a solid state image pickup apparatus including a first semiconductor substrate and a second semiconductor substrate which are bonded to each other, and a buried portion formed in a peripheral portion of the apparatus with a depth of a bonded surface of the first semiconductor substrate and the second semiconductor substrate in such a manner that the bonded surface of the first semiconductor substrate and the second semiconductor substrate is not exposed.Type: ApplicationFiled: January 23, 2015Publication date: July 30, 2015Inventors: Kenta Nojima, Kengo Kotoo, Hirotaka Yoshioka, Kenta Ikeda