Patents by Inventor Kengo Kurose

Kengo Kurose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12283330
    Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: April 22, 2025
    Assignee: KIOXIA CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kiwamu Watanabe, Kengo Kurose
  • Patent number: 12190960
    Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: January 7, 2025
    Assignee: Kioxia Corporation
    Inventors: Kengo Kurose, Masanobu Shirakawa, Hideki Yamada, Marie Takada
  • Patent number: 12117902
    Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: October 15, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Kengo Kurose, Masanobu Shirakawa, Marie Takada
  • Patent number: 12094541
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: September 17, 2024
    Assignee: Kioxia Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kengo Kurose, Marie Takada, Ryo Yamaki, Kiyotaka Iwasaki, Yoshihisa Kojima
  • Patent number: 11755236
    Abstract: According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: September 12, 2023
    Assignee: Kioxia Corporation
    Inventors: Kengo Kurose, Masanobu Shirakawa, Naomi Takeda, Hideki Yamada
  • Patent number: 11756642
    Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: September 12, 2023
    Assignee: Kioxia Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kiwamu Watanabe, Kengo Kurose
  • Patent number: 11698834
    Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: July 11, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Kengo Kurose, Masanobu Shirakawa, Marie Takada
  • Patent number: 11609814
    Abstract: A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: March 21, 2023
    Assignee: Kioxia Corporation
    Inventors: Kengo Kurose, Masanobu Shirakawa
  • Patent number: 11514986
    Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 29, 2022
    Assignee: Kioxia Corporation
    Inventors: Kengo Kurose, Masanobu Shirakawa, Hideki Yamada, Marie Takada
  • Patent number: 11334432
    Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: May 17, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Kengo Kurose, Masanobu Shirakawa, Marie Takada
  • Patent number: 11195585
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: December 7, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kengo Kurose, Marie Takada, Ryo Yamaki, Kiyotaka Iwasaki, Yoshihisa Kojima
  • Patent number: 11152075
    Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: October 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kiwamu Watanabe, Kengo Kurose
  • Patent number: 11099931
    Abstract: A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 24, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Kengo Kurose, Masanobu Shirakawa
  • Patent number: 10866860
    Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: December 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kengo Kurose, Masanobu Shirakawa, Marie Takada
  • Publication number: 20200090763
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.
    Type: Application
    Filed: March 11, 2019
    Publication date: March 19, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kengo Kurose, Marie Takada, Ryo Yamaki, Kiyotaka Iwasaki, Yoshihisa Kojima
  • Publication number: 20150084816
    Abstract: According to one embodiment, an electronic device includes a housing, an antenna, a first shield member, and a first spacer. The housing includes a first wall. The first wall includes an electromagnetic wave-transmissive material. The antenna is configured to overlap, in part, with the electromagnetic wave-transmissive material. The first shield member is located at a side of the antenna opposite the electromagnetic wave-transmissive material. The first spacer is located between the antenna and the first shield member.
    Type: Application
    Filed: June 26, 2014
    Publication date: March 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kengo Kurose, Heiwa Matsuoka, Ippei Kashiwagi, Tomohiro Wada, Isao Okutsu
  • Publication number: 20150070856
    Abstract: According to one embodiment, an electronic device includes a component, a connector, a flexible printed circuit board and a tab. The component includes a first face, a second face, and an edge. The connector is configured to face the first face. The flexible printed circuit board includes a first portion configured to face the second face, a second portion configured to face the first face, a bent third portion between the first portion and the second portion and configured to face the edge, and a terminal provided to the second portion and configured to be connected to the connector. The tab includes an attachment portion and an extension portion. The extension portion is configured to be attached to the flexible printed circuit board. The extension portion extends from the attachment portion toward the terminal along the flexible printed circuit board.
    Type: Application
    Filed: June 5, 2014
    Publication date: March 12, 2015
    Inventors: Tomohiro Wada, Kengo Kurose, Shinichi Fujiwara, Satoru Yasui, Shigenori Miyagawa
  • Patent number: 8830332
    Abstract: According to one embodiment, an electronic device receives a broadcast signal includes a high-speed transmission channel and a low-speed transmission channel. The electronic device estimates a CN when the electronic device is in an environment corresponding to a stationary state, based on a measured reception power, reception sensitivity required for receiving a broadcast service of the high-speed transmission channel and a necessary CN required for receiving the broadcast service of the high-speed transmission channel, and controls a processing of switching a demodulation target between the high-speed transmission channel and the low-speed transmission channel, based on a difference between the estimated CN and the measured CN.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kengo Kurose, Yuki Hayashi
  • Patent number: 8792849
    Abstract: According to one embodiment, a near field radio communication apparatus, as described in embodiments, comprises a signal receiving unit configured to convert a radio signal into an electric signal an information obtaining unit configured to obtain information from a signal output from the signal receiving unit and an operating power supplying unit configured to supply an operating power to the information obtaining unit if a voltage level of the electric signal output from the signal receiving unit varies to he equal to or higher than a preset threshold value.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kengo Kurose, Takashi Minemura
  • Patent number: 8787963
    Abstract: According to one embodiment, a mobile wireless terminal apparatus includes a first communication module, a second communication module, and a controller. The first communication module is configured to detect a beacon signal from a wireless signal transmitted from the base station to a service area, and to determine movement into a new service area and movement to an outside of the service area, based on a variation of a reception timing of the beacon signal. The second communication module is configured to receive a wireless signal transmitted from the base station and to communicate with the base station by acquiring identification information of the base station from the wireless signal. The controller is configured to activate the second communication module and cause the second communication module to acquire the identification information, when the movement to the new service area is determined by the first communication module.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kengo Kurose, Yuki Hayashi