Patents by Inventor Kengo Kurose
Kengo Kurose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230360714Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.Type: ApplicationFiled: July 18, 2023Publication date: November 9, 2023Applicant: KIOXIA CORPORATIONInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Kiwamu WATANABE, Kengo KUROSE
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Publication number: 20230297473Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.Type: ApplicationFiled: May 26, 2023Publication date: September 21, 2023Applicant: KIOXIA CORPORATIONInventors: Kengo KUROSE, Masanobu SHIRAKAWA, Marie TAKADA
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Patent number: 11756642Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.Type: GrantFiled: September 15, 2021Date of Patent: September 12, 2023Assignee: Kioxia CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kiwamu Watanabe, Kengo Kurose
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Patent number: 11755236Abstract: According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.Type: GrantFiled: March 15, 2021Date of Patent: September 12, 2023Assignee: Kioxia CorporationInventors: Kengo Kurose, Masanobu Shirakawa, Naomi Takeda, Hideki Yamada
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Patent number: 11698834Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.Type: GrantFiled: April 12, 2022Date of Patent: July 11, 2023Assignee: KIOXIA CORPORATIONInventors: Kengo Kurose, Masanobu Shirakawa, Marie Takada
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Patent number: 11609814Abstract: A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.Type: GrantFiled: July 28, 2021Date of Patent: March 21, 2023Assignee: Kioxia CorporationInventors: Kengo Kurose, Masanobu Shirakawa
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Publication number: 20230047861Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.Type: ApplicationFiled: October 28, 2022Publication date: February 16, 2023Applicant: Kioxia CorporationInventors: Kengo KUROSE, Masanobu SHIRAKAWA, Hideki YAMADA, Marie TAKADA
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Patent number: 11514986Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.Type: GrantFiled: March 16, 2021Date of Patent: November 29, 2022Assignee: Kioxia CorporationInventors: Kengo Kurose, Masanobu Shirakawa, Hideki Yamada, Marie Takada
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Publication number: 20220245030Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.Type: ApplicationFiled: April 12, 2022Publication date: August 4, 2022Applicant: KIOXIA CORPORATIONInventors: Kengo KUROSE, Masanobu SHIRAKAWA, Marie TAKADA
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Patent number: 11334432Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.Type: GrantFiled: November 6, 2020Date of Patent: May 17, 2022Assignee: KIOXIA CORPORATIONInventors: Kengo Kurose, Masanobu Shirakawa, Marie Takada
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Publication number: 20220066688Abstract: According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.Type: ApplicationFiled: March 15, 2021Publication date: March 3, 2022Applicant: Kioxia CorporationInventors: Kengo KUROSE, Masanobu SHIRAKAWA, Naomi TAKEDA, Hideki YAMADA
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Publication number: 20220044738Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.Type: ApplicationFiled: October 27, 2021Publication date: February 10, 2022Applicant: Toshiba Memory CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Kengo KUROSE, Marie TAKADA, Ryo YAMAKI, Kiyotaka IWASAKI, Yoshihisa KOJIMA
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Publication number: 20220028460Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.Type: ApplicationFiled: March 16, 2021Publication date: January 27, 2022Applicant: Kioxia CorporationInventors: Kengo KUROSE, Masanobu SHIRAKAWA, Hideki YAMADA, Marie TAKADA
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Publication number: 20220005537Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.Type: ApplicationFiled: September 15, 2021Publication date: January 6, 2022Applicant: Toshiba Memory CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Kiwamu WATANABE, Kengo KUROSE
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Patent number: 11195585Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.Type: GrantFiled: March 11, 2019Date of Patent: December 7, 2021Assignee: Toshiba Memory CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kengo Kurose, Marie Takada, Ryo Yamaki, Kiyotaka Iwasaki, Yoshihisa Kojima
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Publication number: 20210357289Abstract: A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.Type: ApplicationFiled: July 28, 2021Publication date: November 18, 2021Inventors: Kengo KUROSE, Masanobu SHIRAKAWA
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Patent number: 11152075Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.Type: GrantFiled: March 6, 2019Date of Patent: October 19, 2021Assignee: Toshiba Memory CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kiwamu Watanabe, Kengo Kurose
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Patent number: 11099931Abstract: A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.Type: GrantFiled: February 26, 2020Date of Patent: August 24, 2021Assignee: KIOXIA CORPORATIONInventors: Kengo Kurose, Masanobu Shirakawa
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Publication number: 20210096949Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.Type: ApplicationFiled: November 6, 2020Publication date: April 1, 2021Applicant: Toshiba Memory CorporationInventors: Kengo KUROSE, Masanobu SHIRAKAWA, Marie TAKADA
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Publication number: 20200409788Abstract: A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.Type: ApplicationFiled: February 26, 2020Publication date: December 31, 2020Inventors: Kengo KUROSE, Masanobu SHIRAKAWA