Abstract: A polyimide resin that is a copolymer of an amino compound (A) and a tetrabasic acid dianhydride (B). The amino compound (A) includes a straight chain aliphatic diamino compound (a1) and an aromatic diamino compound (a2). The straight chain aliphatic diamino compound (a1) includes amino groups at both terminals, 1 to 4 methyl groups and/or ethyl groups in a side chain and 17 to 24 carbon atom in a main chain.

Abstract: A polymide resin is the product of a reaction between an imidized compound (P) of a polyamic acid resin with a compound (C) having a functional group, that can react with a phenolic hydroxyl group, and an ethylenically unsaturated double bond group. The polyamic acid resin is a copolymer of amino compounds (A) and a tetrabasic acid dianhydride (B). Amino compounds (A) contain an aminophenol compound (a1) having at least two amino groups per molecule, an aliphatic diamino compound (a2) having 6-36 carbon atoms, and an aromatic diamino compound (a3) having no phenolic hydroxyl group.

Abstract: Provided are an antibody or fragment thereof specifically bindable to the NTD or CTD of the N protein of SARS-CoV-2, and use of the antibody or fragment thereof. An antibody or fragment thereof specifically bindable to the amino acid sequence of SEQ ID NO: 1 or 2 is disclosed.

Abstract: A curable resin composition containing: a maleimide resin (A) having a cyclic imide bond obtained by reacting a diamine (a-1) derived from a dimer acid, a tetracarboxylic dianhydride (a-2), and a maleic anhydride; a maleimide resin (B) represented by the following formula (1); and a curing accelerator (D), in which the components (A), (B), and (D) are compatible with one another: in the formula (1), plural R each independently represent a hydrogen atom or an alkyl group having 1 to 5 carbon atoms. m represents an integer of 0 to 3. n represents the number of repetitions, and an average value thereof is 1<n<5.

Abstract: A resin composition contains a maleimide compound (I) that is the product of a reaction between a diamine (a-1) derived from a dimer acid and maleic anhydride, and a reactive polycarboxylic acid resin (II) that is the product of a reaction between a reactive epoxycarboxylate resin, the reactive epoxycarboxylate resin being the product of a reaction between an epoxy resin (b-1) and a compound (b-2) having a polymerizable ethylenically unsaturated group and a carboxy group together in one molecule, and a polybasic acid anhydride (b-3).

Abstract: The present application provides a resin-molded capacitor such that heat generated by a capacitor element can be efficiently dissipated, and a power conversion device. The resin-molded capacitor includes a first bus bar and a second bus bar joined to a first capacitor electrode and a second capacitor electrode respectively of a capacitor element, an insulating member joined to at least one of the first capacitor electrode and the second capacitor electrode or at least one of the first bus bar and the second bus bar, and an electrically conductive member joined to the insulating member.

Abstract: In order to achieve small noise and small vibration, as well as a small size and a low cost in a power converter including a capacitor module, there is provided a power converter including a power module and a capacitor module. The capacitor module includes: a plurality of capacitor elements each having a flat wound surface; an exterior case; a resin filler; and a restraint point. The exterior case has arranged therein an inclusion serving as a beam in a direction orthogonal to a flat wound surface of at least one capacitor element of the plurality of capacitor elements, and the at least one capacitor element, and the restraint point is arranged substantially in front of the flat wound surface via the inclusion.

Abstract: The present application provides a resin-molded capacitor such that heat generated by a capacitor element can be efficiently dissipated, and a power conversion device. The resin-molded capacitor includes a first bus bar and a second bus bar joined to a first capacitor electrode and a second capacitor electrode respectively of a capacitor element, an insulating member joined to at least one of the first capacitor electrode and the second capacitor electrode or at least one of the first bus bar and the second bus bar, and an electrically conductive member joined to the insulating member.

Abstract: In order to achieve small noise and small vibration, as well as a small size and a low cost in a power converter including a capacitor module, there is provided a power converter including a power module and a capacitor module. The capacitor module includes: a plurality of capacitor elements each having a flat wound surface; an exterior case; a resin filler; and a restraint point. The exterior case has arranged therein an inclusion serving as a beam in a direction orthogonal to a flat wound surface of at least one capacitor element of the plurality of capacitor elements, and the at least one capacitor element, and the restraint point is arranged substantially in front of the flat wound surface via the inclusion.

Abstract: In a power conversion apparatus including first to fourth semiconductor switching elements connected in series across both terminals of a high voltage-side capacitor, the third and fourth semiconductor switching elements are connected across both terminals of a low voltage-side capacitor via a reactor, and both terminals of the second and third semiconductor switching elements are connected across a charging-discharging capacitor. This charging-discharging capacitor includes a plurality of capacitor elements connected in parallel via a first wiring and a second wiring. Inductance components or capacitance components of the plurality of capacitor elements when viewed from an outflow-inflow portion of the first wiring and an outflow-inflow portion of the second wiring are different from each other such that the charging-discharging capacitor does not have a parallel resonance point in a driving frequency band but has a parallel resonance point in a noise frequency band.

Abstract: In a power conversion apparatus including first to fourth semiconductor switching elements connected in series across both terminals of a high voltage-side capacitor, the third and fourth semiconductor switching elements are connected across both terminals of a low voltage-side capacitor via a reactor, and both terminals of the second and third semiconductor switching elements are connected across a charging-discharging capacitor. This charging-discharging capacitor includes a plurality of capacitor elements connected in parallel via a first wiring and a second wiring. Inductance components or capacitance components of the plurality of capacitor elements when viewed from an outflow-inflow portion of the first wiring and an outflow-inflow portion of the second wiring are different from each other such that the charging-discharging capacitor does not have a parallel resonance point in a driving frequency band but has a parallel resonance point in a noise frequency band.

Abstract: A 3D decoding apparatus according to the present invention includes: a decoding unit which decodes left-eye and right-eye code signals to generate left-eye and right-eye decode signals; an error determining unit which determines an error of the left-eye and the right-eye code signals; an output determining unit which determines, when there is an error in one of the left-eye and the right-eye code signals, whether the one of the code signals that is determined as including an error has an error data mount equal to or greater than a first threshold; and an output unit which outputs neither the left-eye nor the right-eye code signal when the error data amount is smaller than the first threshold, and outputs only the decode signal obtained by decoding the other of the code signals when the error data amount is equal to or greater than the first threshold.

Abstract: A 3D video processing apparatus according to an aspect of the present invention includes an offset value complementing unit which complements an offset value of the first picture, by assigning a value which is equal to or greater than the first offset value and equal to or smaller than the second offset value, the first offset value representing the smaller one of the offset value assigned to the second picture temporally preceding the first picture and the offset value assigned to the third picture temporally succeeding the first picture, and the second offset value representing the larger one of the offset value assigned to the second picture and the offset value assigned to the third picture.

Abstract: A 3D video processor that outputs a left-eye image and a right-eye image to be superimposed on main video includes: a left-eye object processing unit that outputs the left-eye image; a right-eye object processing unit that outputs the right-eye image; and an image output control unit that controls the left-eye object processing unit and the right-eye object processing unit so that the images are synchronously outputted. The left-eye object processing unit determines if image output preparation of the left-eye image is completed. The right-eye object processing unit determines if image output preparation of the right-eye image is completed. The image output control unit instructs to skip the output of both the images, when the image output preparation of one of the left-eye image and the right-eye image is not completed.

Abstract: A 3D decoding apparatus according to the present invention includes: a decoding unit which decodes left-eye and right-eye code signals to generate left-eye and right-eye decode signals; an error determining unit which determines an error of the left-eye and the right-eye code signals; an output determining unit which determines, when there is an error in one of the left-eye and the right-eye code signals, whether the one of the code signals that is determined as including an error has an error data mount equal to or greater than a first threshold; and an output unit which outputs neither the left-eye nor the right-eye code signal when the error data amount is smaller than the first threshold, and outputs only the decode signal obtained by decoding the other of the code signals when the error data amount is equal to or greater than the first threshold.

Abstract: A 3D decoding apparatus according to the present invention includes: a decoding unit which decodes left-eye and right-eye code signals to generate left-eye and right-eye decode signals; an error determining unit which determines an error of the left-eye and the right-eye code signals; an output determining unit which determines, when there is an error in one of the left-eye and the right-eye code signals, whether the one of the code signals that is determined as including an error has an error data mount equal to or greater than a first threshold; and an output unit which outputs neither the left-eye nor the right-eye code signal when the error data amount is smaller than the first threshold, and outputs only the decode signal obtained by decoding the other of the code signals when the error data amount is equal to or greater than the first threshold.

Abstract: A 3D video processor that outputs a left-eye image and a right-eye image to be superimposed on main video includes: a left-eye object processing unit that outputs the left-eye image; a right-eye object processing unit that outputs the right-eye image; and an image output control unit that controls the left-eye object processing unit and the right-eye object processing unit so that the images are synchronously outputted. The left-eye object processing unit determines if image output preparation of the left-eye image is completed. The right-eye object processing unit determines if image output preparation of the right-eye image is completed. The image output control unit instructs to skip the output of both the images, when the image output preparation of one of the left-eye image and the right-eye image is not completed.

Abstract: A 3D video processor that outputs a left-eye image and a right-eye image to be superimposed on main video includes: a left-eye object processing unit that outputs the left-eye image; a right-eye object processing unit that outputs the right-eye image; and an image output control unit that controls the left-eye object processing unit and the right-eye object processing unit so that the left-eye image and the right-eye image are synchronously outputted. The left-eye object processing unit determines whether or not image output preparation of the left-eye image is completed. The right-eye object processing unit determines whether or not image output preparation of the right-eye image is completed. The image output control unit instructs to skip the output of both the left-eye image and the right-eye image, when the image output preparation of one of the left-eye image and the right-eye image is not completed.

Abstract: A 3D decoding apparatus according to the present invention includes: a decoding unit which decodes left-eye and right-eye code signals to generate left-eye and right-eye decode signals; an error determining unit which determines an error of the left-eye and the right-eye code signals; an output determining unit which determines, when there is an error in one of the left-eye and the right-eye code signals, whether the one of the code signals that is determined as including an error has an error data mount equal to or greater than a first threshold; and an output unit which outputs neither the left-eye nor the right-eye code signal when the error data amount is smaller than the first threshold, and outputs only the decode signal obtained by decoding the other of the code signals when the error data amount is equal to or greater than the first threshold.

Abstract: A 3D video processing apparatus according to an aspect of the present invention includes an offset value complementing unit which complements an offset value of the first picture, by assigning a value which is equal to or greater than the first offset value and equal to or smaller than the second offset value, the first offset value representing the smaller one of the offset value assigned to the second picture temporally preceding the first picture and the offset value assigned to the third picture temporally succeeding the first picture, and the second offset value representing the larger one of the offset value assigned to the second picture and the offset value assigned to the third picture.