Abstract: Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and third capacitors are electrically coupled in common to one another. The second electrodes of the first and third capacitors are electrically coupled in common to each other. The second electrode of the second capacitor is electrically insulated from the second electrodes of the first and third capacitors.

Abstract: Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and third capacitors are electrically coupled in common to one another. The second electrodes of the first and third capacitors are electrically coupled in common to each other. The second electrode of the second capacitor is electrically insulated from the second electrodes of the first and third capacitors.

Abstract: Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and third capacitors are electrically coupled in common to one another. The second electrodes of the first and third capacitors are electrically coupled in common to each other. The second electrode of the second capacitor is electrically insulated from the second electrodes of the first and third capacitors.

Abstract: Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and third capacitors are electrically coupled in common to one another. The second electrodes of the first and third capacitors are electrically coupled in common to each other. The second electrode of the second capacitor is electrically insulated from the second electrodes of the first and third capacitors.

Abstract: A semiconductor memory device includes: first and second memory mats; first and second local input output lines coupled to the first memory mat via a first amplifier circuit; third and fourth local input output lines different from the first and second local input output lines, third and fourth local input output lines coupled to the second memory mat via a second amplifier circuit; a third amplifier circuit coupled between the first local input output line and a first main input output line; a fourth amplifier circuit coupled between the third local input output line and a second main input output line different from the first main input output line; and a first switch coupled between the second and third local input output lines and connecting the second local input output line to the fourth amplifier circuit when the first memory mat is activated and the second memory mat is not activated.

Abstract: A semiconductor memory device includes: first and second memory mats; first and second local input output lines coupled to the first memory mat via a first amplifier circuit; third and fourth local input output lines different from the first and second local input output lines, third and fourth local input output lines coupled to the second memory mat via a second amplifier circuit; a third amplifier circuit coupled between the first local input output line and a first main input output line; a fourth amplifier circuit coupled between the third local input output line and a second main input output line different from the first main input output line; and a first switch coupled between the second and third local input output lines and connecting the second local input output line to the fourth amplifier circuit when the first memory mat is activated and the second memory mat is not activated.

Abstract: A semiconductor memory device has a redundancy function using a fuse block arranged in a window. The fuse block includes a plurality of fuse elements selectively cut by a laser beam in the window for decoding the input address of a defective memory cell. Each fuse element has a pair of parallel lead sections, and a bridge section bridging the ends of the lead sections and disposed for laser cutting. The longer sides of the window can be reduced in size for reduction of the occupied area for the pitch of signal lines and thus the chip area.

Abstract: Disclosed hereby is a technique to compensate for variations of the logical thresholds of the plurality of input initial stage circuits of a semiconductor integrated circuit due to the parasitic resistances of wiring layers (the power supply wiring layer and the ground wiring layer) for the supply of a fixed potential.The dimensions of the transistors constituting the input initial stage circuits, for instance the channel widths of the N-channel MOSFET's of CMOS inverters, are enlarged to compensate for an increase in the logical thresholds due to the parasitic resistances of the ground wiring layer. The unevenness of logical thresholds of the plurality of input initial stage circuits due to their respective positions in the semiconductor chip can be thereby reduced.

Abstract: A cache memory system having an improved area addressing scheme for rewriting is disclosed. The cache memory system comprises a cache memory having a plurality of memory areas, a first detection circuit for designating the least recently accessed area by a CPU, a second detection circuit for detecting that the least recently accessed memory area is not designated and a control circuit for forcibly selecting a predetermined one memory area for rewriting when the least recently accessed memory area is not designated.