Abstract: A secondary battery that can suppress performance deterioration due to temperature rise and has excellent incombustibility is provided. The secondary battery contains two or more cells each including a cell stack that includes a positive electrode having a positive electrode terminal, a negative electrode having a negative electrode terminal, a separator interposed between the positive electrode and the negative electrode, and an electrolyte held by the separator and contains a second heat storage sheet including an incombustible layer. The second heat storage sheet is disposed between the two or more cells.

Abstract: A heat storage sheet includes a resin matrix and a heat storage material that is dispersed in the resin matrix. The heat storage sheet has a tensile strength of 0.1 MPa or more and a tensile elongation at break of 10% or more, as measured in accordance with the method of JIS K6251.

Abstract: A heat-storage composition includes a resin and a heat storage material. The composition has a viscosity of 100 to 1,000 dPa·s, as measured with a cylinder-type rotational viscometer. The composition also has a storage elastic modulus (G?) of 3 Pa or more at an angular frequency of 1 rad/s, as measured by a dynamic viscoelasticity measurement method at a temperature of 25° C. and at a strain of 0.1%.

Abstract: A heat storage molded body includes a heat storage medium dispersed in a resin matrix, wherein the resin matrix includes a resin composition containing a thermoplastic resin and a non-phthalate plasticizer, and wherein an absorbed amount of the non-phthalate plasticizer per 100 parts by mass of the heat storage medium when the non-phthalate plasticizer is mixed with the heat storage medium as measured in accordance with JIS K5101-13-1 is 150 parts by mass or less.

Abstract: A heat storage molded body includes a heat storage medium dispersed in a resin matrix, wherein the resin matrix includes a resin composition containing a thermoplastic resin and a non-phthalate plasticizer, and wherein the Hansen Solubility Parameter (HSP) distance between the non-phthalate plasticizer and the heat storage medium is 6 or more.

Abstract: A heat-storage composition includes a resin and a heat storage material. The composition has a viscosity of 100 to 1,000 dPa·s, as measured with a cylinder-type rotational viscometer. The composition also has a storage elastic modulus (G?) of 3 Pa or more at an angular frequency of 1 rad/s, as measured by a dynamic viscoelasticity measurement method at a temperature of 25° C. and at a strain of 0.1%.

Abstract: A heat storage sheet includes a resin matrix and a heat storage material that is dispersed in the resin matrix. The heat storage sheet has a tensile strength of 0.1 MPa or more and a tensile elongation at break of 10% or more, as measured in accordance with the method of JIS K6251.

Abstract: A heat storage laminate includes an inorganic substrate and an organic heat storage layer, wherein the inorganic substrate and the organic heat storage layer are laminated to one another. The inorganic substrate has a thickness of 8 mm or more and a mass reduction ratio of 4% by mass or more, as measured when the inorganic substrate is held at a temperature of 105° C. until a constant mass is obtained.

Abstract: A heat storage molded body includes a heat storage medium dispersed in a resin matrix, wherein the resin matrix includes a resin composition containing a thermoplastic resin and a non-phthalate plasticizer, and wherein the Hansen Solubility Parameter (HSP) distance between the non-phthalate plasticizer and the heat storage medium is 6 or more.

Abstract: A heat storage molded body includes a heat storage medium dispersed in a resin matrix, wherein the resin matrix includes a resin composition containing a thermoplastic resin and a non-phthalate plasticizer, and wherein an absorbed amount of the non-phthalate plasticizer per 100 parts by mass of the heat storage medium when the non-phthalate plasticizer is mixed with the heat storage medium as measured in accordance with JIS K5101-13-1 is 150 parts by mass or less.

Abstract: A test apparatus including a first buffer section and a second buffer section that each buffers fail data and address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using an RMW process; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section.

Abstract: A test apparatus that tests a memory under test, comprising an address fail memory that stores address fail data for each address; a block fail memory that stores block fail data for each block; a reading section that reads the address fail data from the address fail memory for each block; a row fail counter that, for each row address in a group including a plurality of the blocks in the memory under test, counts the fail cells indicated by the address fail data; and a column fail counter that counts the fails cells for each column address.

Abstract: A test apparatus includes a fail memory (AFM) for storing therein fail information in association with each of the addresses of a memory under test and a mark memory (CMM) for storing therein, in association with each of the addresses of the memory under test, validity information indicating whether the fail information stored in the AFM is valid. When the validity information read from the CMM in association with an address under test indicates that the fail information that has been stored in the AFM is invalid, the test apparatus overwrites the fail information stored in the AFM with the fail information that is newly generated by a current test. On the other hand, when the validity information read from the CMM indicates that the fail information is valid, the test apparatus updates the fail information stored in the AFM with the new fail information and writes the updated fail information back into the AFM.

Abstract: A test apparatus comprising a first buffer section and a second buffer section that each buffers fail data and address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using an RMW process; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section.

Abstract: A test apparatus that tests a memory under test, comprising an address fail memory that stores address fail data for each address; a block fail memory that stores block fail data for each block; a reading section that reads the address fail data from the address fail memory for each block; a row fail counter that, for each row address in a group including a plurality of the blocks in the memory under test, counts the fail cells indicated by the address fail data; and a column fail counter that counts the fails cells for each column address.

Abstract: Provided is a test apparatus that tests a memory under test, comprising a logic comparing section that compares output data output from the memory under test to expected value data, for each address of the memory under test, and outputs fail data when the output data does not match the expected value data; a fail analysis memory section that stores the fail data in association with the addresses of the memory under test; and a masking section that counts the pieces of fail data output from the logic comparing section and, when the count value exceeds a preset upper limit fail value, masks the fail data supplied from the logic comparing section to the fail analysis memory section.

Abstract: A test apparatus includes a fail memory (AFM) for storing therein fail information in association with each of the addresses of a memory under test and a mark memory (CMM) for storing therein, in association with each of the addresses of the memory under test, validity information indicating whether the fail information stored in the AFM is valid. When the validity information read from the CMM in association with an address under test indicates that the fail information that has been stored in the AFM is invalid, the test apparatus overwrites the fail information stored in the AFM with the fail information that is newly generated by a current test. On the other hand, when the validity information read from the CMM indicates that the fail information is valid, the test apparatus updates the fail information stored in the AFM with the new fail information and writes the updated fail information back into the AFM.

Abstract: The test apparatus includes: a pattern memory that stores therein data to be outputted to the device under test; a device judgment section that judges whether the device under test passes or fails based on an output signal; the number of data information storage section that stores therein the number of data information based on the number of logic H data included in an input data; a counter that receives output data outputted from the pattern memory to the device under test and counts the number of logic H data included in the output data; a pattern memory judgment section that judges that the data stored in the pattern memory is correct when the number of data information on the input data is corresponding to the number of logic H data counted by the counter and outputs a signal according to this judgment result.

Abstract: A testing apparatus according to the present invention includes: a pattern generator for generating an address signal, a data signal and an expected value signal to be provided to a memory under test; an OR comparator for outputting fail data when an output signal outputted by the memory under test is not matched with the expected value signal; a first FBM for storing the fail data in a first test; a second FBM for accumulating the fail data stored in the first FBM and fail data in a second test and storing therein the same; and a safe analysis section for performing a fail safe analysis on the memory under test with reference to the fail data stored in the first FBM. The first FBM accumulates the fail data stored in the second FBM and the fail data in the third test. The safe analysis section performs a fail safe analysis on the memory under test further with reference to the fail data stored in the second FBM.

Abstract: A test apparatus for testing a device-under-test includes: a pattern generator configured to generate an address signal, a test signal, and an expected value signal; a logical comparator configured to compare an output signal outputted from the device-under-test with the expected value signal. The logical comparator generates a fail signal when the output signal is different from the expected value signal; and a failure analysis memory configured to receive the address signal from the pattern generator and to receive the fail signal from the logical comparator. The failure analysis memory includes: a first storage section configured to store a fail address value that corresponds to the fail signal and a fail data value included in the fail signal as a set of data; and a second storage section configured to read the set of data from the first storage section and to store the fail data value.