Patents by Inventor Kenichi Fukui
Kenichi Fukui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977007Abstract: Siloxane compounds are removed from the atmospheres by silica supporting an organic sulfonic acid compound. The silica with the organic sulfonic acid compound has a specific surface area down to 500 m2/g and up to 750 m2/g and a pore volume down to 0.8 m3/g and up to 1.2 m3/g, both measured by nitrogen gas adsorption method and has a pore diameter down to 4 nm and up to 8 nm, at the peak of differential pore volume measured by nitrogen gas adsorption method. The durability of gas sensing element against siloxanes is improved.Type: GrantFiled: May 1, 2020Date of Patent: May 7, 2024Assignees: FIGARO ENGINEERING INC., NEW COSMOS ELECTRIC CO., LTD., UNIVERSITY PUBLIC CORPORATION OSAKAInventors: Masato Takeuchi, Junpei Furuno, Kenta Fukui, Kenichi Yoshioka, Tatsuya Tanihira, Masakazu Sai, Takafumi Taniguchi, Hirokazu Mitsuhashi
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Patent number: 11036122Abstract: A phase modulation data generating unit according to the present disclosure includes: a first calculating section; and a storage section. The first calculating section calculates basic phase modulation pattern data on the basis of a partial illumination image pattern that makes it possible to generate an intended illumination image pattern having a desired luminance distribution. The basic phase modulation pattern data makes it possible for a light phase modulation device to reconstruct the partial illumination image pattern. The storage section stores the basic phase modulation pattern data calculated by the first calculating section.Type: GrantFiled: April 13, 2018Date of Patent: June 15, 2021Assignee: SONY CORPORATIONInventors: Kenichi Fukui, Yoshihisa Sato
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Publication number: 20200183260Abstract: A phase modulation data generating unit according to the present disclosure includes: a first calculating section; and a storage section. The first calculating section calculates basic phase modulation pattern data on the basis of a partial illumination image pattern that makes it possible to generate an intended illumination image pattern having a desired luminance distribution. The basic phase modulation pattern data makes it possible for a light phase modulation device to reconstruct the partial illumination image pattern. The storage section stores the basic phase modulation pattern data calculated by the first calculating section.Type: ApplicationFiled: April 13, 2018Publication date: June 11, 2020Inventors: KENICHI FUKUI, YOSHIHISA SATO
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Patent number: 10593016Abstract: An image processing unit of the disclosure includes an imaging section that acquires a plurality of partial images as a captured image, by imaging a projection screen provided by a projector through division of the projection screen into a plurality of regions to have partially overlapping imaging regions, and an estimation section that performs an operation a plurality of times on a basis of the captured image, the operation being performed to estimate a projection transformation matrix for linking of the partial images adjacent to each other.Type: GrantFiled: June 9, 2016Date of Patent: March 17, 2020Assignee: SONY CORPORATIONInventor: Kenichi Fukui
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Patent number: 10574952Abstract: This image projection apparatus includes a measurement image that is for measurement of positional displacement between a plurality of colors serving as projection fundamental colors, and a projection section that projects the measurement image toward a projection plane. The measurement image has a plurality of unit images each including graphics of the respective plurality of colors, and the graphics of the respective plurality of colors in each of the unit images have respective barycentric positions that are substantially coincident.Type: GrantFiled: March 21, 2017Date of Patent: February 25, 2020Assignee: SONY CORPORATIONInventors: Kenichi Fukui, Atsuhiro Chiba
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Publication number: 20190141302Abstract: This image projection apparatus includes a measurement image that is for measurement of positional displacement between a plurality of colors serving as projection fundamental colors, and a projection section that projects the measurement image toward a projection plane. The measurement image has a plurality of unit images each including graphics of the respective plurality of colors, and the graphics of the respective plurality of colors in each of the unit images have respective barycentric positions that are substantially coincident.Type: ApplicationFiled: March 21, 2017Publication date: May 9, 2019Inventors: KENICHI FUKUI, ATSUHIRO CHIBA
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Publication number: 20180232855Abstract: An image processing unit of the disclosure includes an imaging section that acquires a plurality of partial images as a captured image, by imaging a projection screen provided by a projector through division of the projection screen into a plurality of regions to have partially overlapping imaging regions, and an estimation section that performs an operation a plurality of times on a basis of the captured image, the operation being performed to estimate a projection transformation matrix for linking of the partial images adjacent to each other.Type: ApplicationFiled: June 9, 2016Publication date: August 16, 2018Applicant: SONY CORPORATIONInventor: KENICHI FUKUI
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Patent number: 7652863Abstract: In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ?V between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.Type: GrantFiled: October 15, 2008Date of Patent: January 26, 2010Assignee: Renesas Technology Corp.Inventors: Takayasu Ito, Mitsuru Hiraki, Satoshi Baba, Kenichi Fukui
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Publication number: 20090039846Abstract: In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ?V between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.Type: ApplicationFiled: October 15, 2008Publication date: February 12, 2009Inventors: Takayasu Ito, Mitsuru Hiraki, Satoshi Baba, Kenichi Fukui
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Patent number: 7450361Abstract: In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ?V between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.Type: GrantFiled: November 30, 2006Date of Patent: November 11, 2008Assignee: Renesas Technology Corp.Inventors: Takayasu Ito, Mitsuru Hiraki, Satoshi Baba, Kenichi Fukui
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Publication number: 20070145922Abstract: In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ?V between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.Type: ApplicationFiled: November 30, 2006Publication date: June 28, 2007Inventors: Takayasu Ito, Mitsuru Hiraki, Satoshi Baba, Kenichi Fukui
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Patent number: 7126872Abstract: In view of controlling overshoot when the power supply is inputted without increase in the area occupied with a chip in a voltage generating circuit mounted over a semiconductor integrated circuit, an internal voltage generating circuit comprises a voltage generating circuit for generating a second voltage from a first voltage supplied from outside, and an output buffer for generating a third voltage corresponding to the second voltage. The third voltage is used as the operation power supply of the internal circuit. Moreover, a first switch for enabling an output node of the second voltage to become conductive to the predetermined potential and a control circuit for turning ON the first switch for the predetermined period in response to input of the first voltage are also provided. An output terminal of the output buffer is not clamped but an output of the voltage generating circuit in the preceding stage is clamped to the predetermined voltage.Type: GrantFiled: October 12, 2004Date of Patent: October 24, 2006Assignee: Renesas Technology Corp.Inventors: Kenichi Fukui, Mitsuru Hiraki, Mitsuhiko Okutsu
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Patent number: 7049797Abstract: In a semiconductor integrated circuit device, having a pair of voltage step-down power supply circuits for active and standby conditions, a first reference voltage is formed by amplifying a fixed voltage formed in a fixed voltage generating circuit with an amplifying circuit which can adjust the voltage gain having a resistance circuit and a switch controlled with a first trimming switch setting signal. An internal step-down voltage, when the internal circuit is in the active condition, is outputted from a first output buffer, which is activated with a first control signal. A second reference voltage is formed by adjusting a combination of threshold voltages of MOSFETs and a switch controlled with a second trimming switch setting signal; and, an internal step-down voltage, when the internal circuit is in the standby condition, is outputted with a second output buffer, which is activated with a second control signal.Type: GrantFiled: October 2, 2003Date of Patent: May 23, 2006Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.Inventors: Kenichi Fukui, Mitsuru Hiraki, Takayasu Ito, Isao Nakamura
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Publication number: 20050083736Abstract: In view of controlling overshoot when the power supply is inputted without increase in the area occupied with a chip in a voltage generating circuit mounted over a semiconductor integrated circuit, an internal voltage generating circuit comprises a voltage generating circuit for generating a second voltage from a first voltage supplied from outside, and an output buffer for generating a third voltage corresponding to the second voltage. The third voltage is used as the operation power supply of the internal circuit. Moreover, a first switch for enabling an output node of the second voltage to become conductive to the predetermined potential and a control circuit for turning ON the first switch for the predetermined period in response to input of the first voltage are also provided. An output terminal of the output buffer is not clamped but an output of the voltage generating circuit in the preceding stage is clamped to the predetermined voltage.Type: ApplicationFiled: October 12, 2004Publication date: April 21, 2005Inventors: Kenichi Fukui, Mitsuru Hiraki, Mitsuhiko Okutsu
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Publication number: 20040155636Abstract: There is provided a semiconductor integrated circuit device which assures high performance and low power consumption through reduction of installation area and realizes automatic voltage adjustment of a couple of voltage step-down power supply circuits for active and standby conditions.Type: ApplicationFiled: October 2, 2003Publication date: August 12, 2004Inventors: Kenichi Fukui, Mitsuru Hiraki, Takayasu Ito, Isao Nakamura
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Patent number: 6584031Abstract: In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.Type: GrantFiled: March 28, 2002Date of Patent: June 24, 2003Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiroki Fujisawa, Kazuhiko Kajigaya, Kenichi Fukui, Toshikazu Tachibana
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Publication number: 20020097628Abstract: In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.Type: ApplicationFiled: March 28, 2002Publication date: July 25, 2002Inventors: Hiroki Fujisawa, Kazuhiko Kajigaya, Kenichi Fukui, Toshikazu Tachibana
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Patent number: 6385118Abstract: In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.Type: GrantFiled: July 19, 2001Date of Patent: May 7, 2002Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiroki Fujisawa, Kazuhiko Kajigaya, Kenichi Fukui, Toshikazu Tachibana
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Publication number: 20010040835Abstract: In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.Type: ApplicationFiled: July 19, 2001Publication date: November 15, 2001Inventors: Hiroki Fujisawa, Kazuhiko Kajigaya, Kenichi Fukui, Toshikazu Tachibana
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Patent number: 6288967Abstract: In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.Type: GrantFiled: December 22, 2000Date of Patent: September 11, 2001Assignee: Hitachi, Ltd.Inventors: Hiroki Fujisawa, Kazuhiko Kajigaya, Kenichi Fukui, Toshikazu Tachibana