Abstract: Interfaces between an Al alloy layer and a Ti-containing layer are present in a through hole formed between a lower layer interconnection and an upper layer interconnection. In the interfaces, resistance element regions are formed through heat treatment. A resistance value between the lower layer interconnection and the upper layer interconnection can be adjusted by means of the resistance element region.

Abstract: A method of manufacturing a semiconductor device which reduces the number of impurity implantations. A buffer film for reducing a quantity of an impurity implantation is provided adjacent to an MIS gate structure over a surface of a semiconductor substrate, and an impurity implantation is carried out over the semiconductor substrate, through the buffer film in a first predetermined region in which the buffer film is provided and directly in a second predetermined region of the substrate. An impurity concentration is reduced in a the first predetermined region in which the impurity implantation is carried out through the buffer film, while the impurity concentration is increased in the second predetermined region in which the buffer film is not provided. Accordingly, a plurality of regions having different impurity concentrations are formed as a source/drain of an MISFET by a one-time impurity implantation. Consequently, the number of the impurity implantations is reduced.

Abstract: It is an object to provide a method of manufacturing a semiconductor device which can reduce the number of impurity implantations. A buffer film (5b) for reducing a quantity of an impurity implantation is provided adjacent to an MIS gate structure (3) over a surface of a semiconductor substrate (1), and an impurity implantation (IP1) is carried out over the semiconductor substrate (1), through the buffer film (5b) in a portion in which the buffer film (5b) is provided. An impurity concentration is reduced in a portion in which the impurity implantation is carried out through the buffer film (5b), while the impurity concentration is increased in a portion in which the buffer film (5b) is not provided. Accordingly, a plurality of regions having different impurity concentrations can be formed as a source/drain of an MISFET by a one-time impurity implantation. Consequently, the number of the impurity implantations can be reduced.