Patents by Inventor Kenichi Hikazutani

Kenichi Hikazutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7468297
    Abstract: A method of manufacturing semiconductor device comprising forms a first impurity diffusion region as a lower electrode of a capacitor in a first area of a semiconductor substrate by implanting impurities at a first dose; forms a second impurity diffusion region in a second area, at the end part of the semiconductor substrate, by implanting impurities at a second dose; and forms, by a thermal oxidation method, a capacitor insulation film having a first thickness on the first impurity diffusion region and forms an oxide film having a second thickness which is thicker than the first thickness on the second area.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: December 23, 2008
    Assignee: Fujitsu Limited
    Inventors: Toshiro Futatsugi, Naoto Horiguchi, Ken-ichi Okabe, Kenichi Hikazutani
  • Publication number: 20050221556
    Abstract: A method of manufacturing semiconductor device comprising forms a first impurity diffusion region as a lower electrode of a capacitor in a first area of a semiconductor substrate by implanting impurities at a first dose; forms a second impurity diffusion region in a second area, at the end part of the semiconductor substrate, by implanting impurities at a second dose; and forms, by a thermal oxidation method, a capacitor insulation film having a first thickness on the first impurity diffusion region and forms an oxide film having a second thickness which is thicker than the first thickness on the second area.
    Type: Application
    Filed: April 6, 2005
    Publication date: October 6, 2005
    Inventors: Toshiro Futatsugi, Naoto Horiguchi, Ken-ichi Okabe, Kenichi Hikazutani
  • Patent number: 6709959
    Abstract: A semiconductor device is fabricated by introducing an impurity element into a Si substrate by an ion implantation process with an energy set such that the depth of a junction formed in the Si substrate by the impurity element is less than about 50 nm, and then annealing the substrate, wherein the method further includes a step of removing an oxide film from a surface of the Si substrate before the step of ion implantation process.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: March 23, 2004
    Assignee: Fujitsu Limited
    Inventors: Masataka Kase, Toshiki Miyake, Mitsuaki Hori, Kenichi Hikazutani, Manabu Nakamura, Takayuki Wada, Yoshikazu Kataoka
  • Publication number: 20020177289
    Abstract: A semiconductor device is fabricated by introducing an impurity element into a Si substrate by an ion implantation process with an energy set such that the depth of a junction formed in the Si substrate by the impurity element is less than about 50 nm, and then annealing the substrate, wherein the method further includes a step of removing an oxide film from a surface of the Si substrate before the step of ion implantation process.
    Type: Application
    Filed: December 28, 1999
    Publication date: November 28, 2002
    Inventors: MASATAKA KASE, TOSHIKI MIYAKE, MITSUAKI HORI, KENICHI HIKAZUTANI, MANABU NAKAMURA, TAKAYUKI WADA, YOSHIKAZU KATAOKA
  • Patent number: 6187600
    Abstract: A surface layer portion of a silicon substrate is etched by using a mixed solution which contains ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O) at a weight ratio of 1:(1.3 to 2.65):(275 to 433). The density of the etch pits which have occurred in a surface of the silicon substrate whose surface layer portion was etched by the etching step is measured. The crystal quality, etc. of the silicon substrate are evaluated before a process for manufacturing semiconductor devices using such silicon substrates, in order to avoid a lowering of the yields of the semiconductor devices.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: February 13, 2001
    Assignee: Fujitsu Limited
    Inventors: Yoichi Fujisawa, Kaoru Ogawa, Kenichi Hikazutani
  • Patent number: 5637528
    Abstract: A method of manufacturing a semiconductor device including the steps of: (a) forming a mask layer of a desired pattern on a silicon substrate surface or on an SiO.sub.2 strain absorbing layer formed on the silicon substrate surface; (b) selectively oxidizing the silicon substrate in a dry oxygen atmosphere by using the mask layer as an oxidation mask; and (c) selectively oxidizing the silicon substrate in an atmosphere of dry oxygen mixed with gas containing halogen element, wherein a field oxide film having a thickness of 100 nm or more is formed. The first and second oxidizing steps (b) and (c) are preferably performed at temperatures between 950.degree. C. and 1200.degree. C. A field oxide film with a short bird's beak can be formed while maintaining a relatively high oxidation speed and preventing generation of a white ribbon.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: June 10, 1997
    Assignee: Fujitsu Limited
    Inventors: Masaaki Higashitani, Kenichi Hikazutani
  • Patent number: 5057187
    Abstract: Plasma ashing methods, for moving a resist material formed on a ground layer of a semiconductor device during fabrication of said semiconductor, are performed by using one of three kinds of reactant gases each composed of three different gases. Plasma ashing is performed: at an ashing rate of 0.5 .mu.m/min at 160.degree. C. and with an activation energy of 0.4 eV when a reactant gas composed of oxygen, water vapor and nitrogen is used; at an ashing rate of 0.5 .mu.m/min at 140.degree. C., with an activation energy of 0.38 eV and without etching the ground layer when a reactant gas composed of oxygen, water vapor and tetrafluoromethane is used; and at an ashing rate of 0.5 .mu.m/min at 140.degree. C., with an activation energy of 0.4 eV when a reactant gas composed of oxygen, hydrogen and nitrogen is used.
    Type: Grant
    Filed: May 18, 1990
    Date of Patent: October 15, 1991
    Assignee: Fujitsu Ltd.
    Inventors: Keisuke Shinagawa, Shuzo Fujimura, Kenichi Hikazutani
  • Patent number: 4983254
    Abstract: A process for stripping an organic material, which comprises forming gases including a gas containing oxygen and a gas containing a halogen into plasma in a plasma chamber, and supplying an active species of the halogen in the gas formed plasma to a reaction chamber to strip the organic material in the reaction chamber, wherein one mole or more of water vapor based upon two moles of the halogen molecule is fed to the reaction chamber, and the active species of the halogen are removed before contact thereof with the organic material.
    Type: Grant
    Filed: January 4, 1990
    Date of Patent: January 8, 1991
    Assignee: Fujitsu Limited
    Inventors: Shuzo Fujimura, Keisuke Shinagawa, Kenichi Hikazutani
  • Patent number: 4980022
    Abstract: A method removes a first layer of an organic matter which is formed on a second layer, where the first layer is subjected to an ion implantation. The method includes the steps of generating a plasma by exciting a gas which includes H.sub.2 O using a high-frequency energy source, and removing the first layer within the plasma.
    Type: Grant
    Filed: March 5, 1990
    Date of Patent: December 25, 1990
    Assignee: Fujitsu Limited
    Inventors: Shuzo Fujimura, Kenichi Hikazutani
  • Patent number: 4961820
    Abstract: Plasma ashing methods, for moving a resist material formed on a ground layer of a semiconductor device during fabrication of said semiconductor, are performed by using one of three kinds of reactant gases each composed of three different gases. Plasma ashing is performed: at an ashing rate of 0.5 .mu.m/min at 160.degree. C. and with an activation energy of 0.4 eV when a reactant gas composed of oxygen, water vapor and nitrogen is used; at an ashing rate of 0.5 .mu.m/min at 140.degree. C., with an activation energy of 0.38 eV and without etching the ground layer when a reactant gas composed of oxygen, water vapor and tetrafluoromethane is used; and at an ashing rate of 0.5 .mu.m/min at 140.degree. C., with an activation energy of 0.4 eV when a reactant gas composed of oxygen, hydrogen and nitrogen is used.
    Type: Grant
    Filed: June 5, 1989
    Date of Patent: October 9, 1990
    Assignee: Fujitsu Limited
    Inventors: Keisuke Shinagawa, Shuzo Fujimura, Kenichi Hikazutani