Patents by Inventor Kenichi Hirashiki
Kenichi Hirashiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8797108Abstract: A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor; and a second capacitor.Type: GrantFiled: February 7, 2012Date of Patent: August 5, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Hirashiki, Shinichiro Ishizuka, Nobuyuki Itoh
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Patent number: 8456227Abstract: In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.Type: GrantFiled: March 14, 2011Date of Patent: June 4, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Hirashiki, Norio Hagiwara, Tsutomu Nakashima, Minoru Nagata
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Publication number: 20120139651Abstract: A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor; and a second capacitor.Type: ApplicationFiled: February 7, 2012Publication date: June 7, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenichi HIRASHIKI, Shinichiro ISHIZUKA, Nobuyuki ITOH
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Patent number: 8134421Abstract: A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor.Type: GrantFiled: May 19, 2010Date of Patent: March 13, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Hirashiki, Shinichiro Ishizuka, Nobuyuki Itoh
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Publication number: 20110304387Abstract: In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.Type: ApplicationFiled: March 14, 2011Publication date: December 15, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenichi Hirashiki, Norio Hagiwara, Tsutomu Nakashima, Minoru Nagata
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Publication number: 20110234311Abstract: According to one embodiment, a current detection circuit is provided with: a NMOS transistor, whose control signal is given to a gate electrode, whose source electrode is connected to a ground line, and whose drain electrode is connected to an input/output terminal; a first PMOS transistor, in which the control signal is given to a gate electrode, and whose drain electrode is connected to the input/output terminal and the drain electrode of the NMOS transistor; and a second PMOS transistor, whose drain electrode is connected to the source electrode of the first PMOS transistor, and a first supply voltage is given to a source electrode. A detection section detects whether or not a current has changed at the input/output terminal from a change in current flowing through the second PMOS transistor.Type: ApplicationFiled: March 14, 2011Publication date: September 29, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenichi Hirashiki, Minoru Nagata
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Publication number: 20110050354Abstract: A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor.Type: ApplicationFiled: May 19, 2010Publication date: March 3, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenichi HIRASHIKI, Shinichiro ISHIZUKA, Nobuyuki ITOH