Patents by Inventor Kenichi Ide

Kenichi Ide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978665
    Abstract: A semiconductor manufacturing method includes forming a concave portion in a layer provided above a substrate from a top surface of the layer downwards, the layer including an insulation layer at least partially. The method includes forming a silicon film on an inner surface of the concave portion. The method includes exposing the silicon film to a raw material gas of metal and an inhibitor gas that inhibits growth of the metal at a first temperature, to replace a first portion of the silicon film located in an upper-end side portion of the concave portion with a first conductive film containing the metal. The method includes exposing the silicon film to the raw material gas and the inhibitor gas at a second temperature lower than the first temperature, to replace a second portion of the silicon film with a second conductive film containing the metal.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: May 7, 2024
    Assignee: Kioxia Corporation
    Inventor: Kenichi Ide
  • Patent number: 11903198
    Abstract: A semiconductor device according to an embodiment includes a stacked body including a plurality of conductive layers and a plurality of first insulation layers alternately stacked in a first direction. The conductive layers each include a first metal layer and a second metal layer. The first metal layer contains a first metal element and a substance that is chemically reactive with a material gas containing the first metal element. The second metal layer contains the first metal element and has a lower content of the substance than the first metal layer. The first metal layer is disposed between the first insulation layers and the second metal layer.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: February 13, 2024
    Assignee: Kioxia Corporation
    Inventors: Kenichi Ide, Hiroko Tahara
  • Publication number: 20220293464
    Abstract: A semiconductor manufacturing method includes forming a concave portion in a layer provided above a substrate from a top surface of the layer downwards, the layer including an insulation layer at least partially. The method includes forming a silicon film on an inner surface of the concave portion. The method includes exposing the silicon film to a raw material gas of metal and an inhibitor gas that inhibits growth of the metal at a first temperature, to replace a first portion of the silicon film located in an upper-end side portion of the concave portion with a first conductive film containing the metal. The method includes exposing the silicon film to the raw material gas and the inhibitor gas at a second temperature lower than the first temperature, to replace a second portion of the silicon film with a second conductive film containing the metal.
    Type: Application
    Filed: September 8, 2021
    Publication date: September 15, 2022
    Applicant: Kioxia Corporation
    Inventor: Kenichi IDE
  • Publication number: 20220077185
    Abstract: A semiconductor device according to an embodiment includes a stacked body including a plurality of conductive layers and a plurality of first insulation layers alternately stacked in a first direction. The conductive layers each include a first metal layer and a second metal layer. The first metal layer contains a first metal element and a substance that is chemically reactive with a material gas containing the first metal element. The second metal layer contains the first metal element and has a lower content of the substance than the first metal layer. The first metal layer is disposed between the first insulation layers and the second metal layer.
    Type: Application
    Filed: June 17, 2021
    Publication date: March 10, 2022
    Applicant: Kioxia Corporation
    Inventors: Kenichi IDE, Hiroko TAHARA
  • Publication number: 20210407905
    Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of first conductive layers that each include tungsten; a plurality of insulating films that include a stacked portion and a first projecting portion projecting; a semiconductor layer extending through an inside of a stacked body; a charge storage layer arranged between the plurality of first conductive layers and the semiconductor layer; a plurality of second conductive layers that are each arranged on the first projecting portion in such a manner as to be in contact with a single first conductive layer and that include silicon containing an impurity; and a plurality of contact plugs that are each provided on a single second conductive layer in such a manner as to be in contact with the single second conductive layer.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 30, 2021
    Applicant: Kioxia Corporation
    Inventors: Takashi SHIMIZU, Takashi FUKUSHIMA, Naomi FUKUMAKI, Hiroko TAHARA, Kenichi IDE
  • Publication number: 20160322377
    Abstract: The memory string includes a plurality of control gate electrodes, a semiconductor layer, and an electric charge accumulating layer. The plurality of control gate electrodes are laminated on a substrate. The semiconductor layer has a longitudinal direction in a direction perpendicular to the substrate. The semiconductor layer opposes the plurality of control gate electrodes. The electric charge accumulating layer is disposed between the control gate electrode and the semiconductor layer. The contact includes a contact layer. The contact layer has a long plate shape whose length in a first direction is longer than a length in a second direction. A lower surface of the contact layer is coupled to the substrate. The contact layer includes a first metal layer and a second metal layer. The first metal layer contains tungsten. The second metal layer is disposed over the first metal layer. The second metal layer contains titanium nitride.
    Type: Application
    Filed: August 25, 2015
    Publication date: November 3, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenichi IDE
  • Patent number: 9041114
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, and a gate insulator arranged on the semiconductor substrate. The device further includes a gate electrode including a semiconductor layer and a metal layer which are sequentially arranged on the gate insulator. The device further includes a contact plug arranged on the gate electrode to penetrate the metal layer, and having a bottom surface at a level lower than an upper surface of the semiconductor layer.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenichi Ide
  • Publication number: 20150005909
    Abstract: A communication device according to an embodiment includes a reception unit, a determination unit, a generation unit, and a transmission unit. The reception unit receives a telegram which is transmitted to a node. The determination unit determines whether or not the telegram which is received by the reception unit includes a command related to a communication path. When the determination unit determines that the telegram does not include the command related to the communication path, the generation unit generates a non-pass signal which indicates that the telegram does not pass through a public line. The transmission unit transmits the non-pass signal which is generated by the generation unit to the node.
    Type: Application
    Filed: December 24, 2013
    Publication date: January 1, 2015
    Applicant: TOSHIBA LIGHTING & TECHNOLOGY CORPORATION
    Inventors: Nobuyuki Monma, Shuichi Kyuma, Kenichi Ide, Keiichi Teramoto, Yoshiki Terashima
  • Publication number: 20140339613
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, and a gate insulator arranged on the semiconductor substrate. The device further includes a gate electrode including a semiconductor layer and a metal layer which are sequentially arranged on the gate insulator. The device further includes a contact plug arranged on the gate electrode to penetrate the metal layer, and having a bottom surface at a level lower than an upper surface of the semiconductor layer.
    Type: Application
    Filed: August 30, 2013
    Publication date: November 20, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenichi IDE
  • Patent number: 8753977
    Abstract: A method for manufacturing a semiconductor device includes dry etching an interlayer insulating layer provided on a foundation layer by using a mask having a plurality of first openings and a plurality of second openings arranged more closely than the first openings to form simultaneously a first hole reaching the foundation layer under each of the first openings and a second hole reaching the foundation layer under the second openings. The first hole reaches the foundation layer without contacting any other first holes. After starting of the dry etching, a plurality of holes are formed under each of the plurality of second openings, and with the progress of the dry etching, the plurality of holes are connected with each other at least at their upper parts including their open ends to form the second hole having an opening area larger than an opening area of the first hole.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Ide
  • Publication number: 20140141620
    Abstract: A method for manufacturing a semiconductor device includes dry etching an interlayer insulating layer provided on a foundation layer by using a mask having a plurality of first openings and a plurality of second openings arranged more closely than the first openings to form simultaneously a first hole reaching the foundation layer under each of the first openings and a second hole reaching the foundation layer under the second openings. The first hole reaches the foundation layer without contacting any other first holes. After starting of the dry etching, a plurality of holes are formed under each of the plurality of second openings, and with the progress of the dry etching, the plurality of holes are connected with each other at least at their upper parts including their open ends to form the second hole having an opening area larger than an opening area of the first hole.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 22, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kenichi IDE
  • Patent number: 8617979
    Abstract: According to one embodiment, a method can include dry etching an interlayer insulating layer provided on a foundation layer by using a mask having a plurality of first openings and a plurality of second openings arranged more closely than the first openings to form simultaneously a first hole reaching the foundation layer under each of the first openings and a second hole reaching the foundation layer under the second openings. The first hole reaches the foundation layer without contacting any other first holes. After starting of the dry etching, a plurality of holes are formed under each of the plurality of second openings, and with the progress of the dry etching, the plurality of holes are connected with each other at least at their upper parts including their open ends to form the second hole having an opening area larger than an opening area of the first hole.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Ide
  • Patent number: 8555687
    Abstract: The present disclosure relates to a hot rolling apparatus for manufacturing a metal plate by hot-rolling-treating a metal material including copper.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: October 15, 2013
    Assignees: IHI Corporation, IHI Metaltech Co., Ltd.
    Inventors: Kengo Ishige, Yasuo Matsunaga, Hiroyuki Otsuka, Kenichi Ide, Masahiro Kuchi, Hisashi Honjou
  • Publication number: 20130063412
    Abstract: According to one embodiment, an electronic device including, an emergency power supply module configured to supply electric power to the display at the time of interruption of a regular power supply, a first communication module configured to perform communication based on a first standard, a second communication module configured to perform communication based on a second standard having a capacity and a transmission speed that are lower than those of the first standard, and a controller configured to drive a display using the emergency power supply module and to switch the communication using the first communication module to the communication using the second communication module.
    Type: Application
    Filed: April 30, 2012
    Publication date: March 14, 2013
    Inventor: Kenichi Ide
  • Publication number: 20120211893
    Abstract: According to one embodiment, a method can include dry etching an interlayer insulating layer provided on a foundation layer by using a mask having a plurality of first openings and a plurality of second openings arranged more closely than the first openings to form simultaneously a first hole reaching the foundation layer under each of the first openings and a second hole reaching the foundation layer under the second openings. The first hole reaches the foundation layer without contacting any other first holes. After starting of the dry etching, a plurality of holes are formed under each of the plurality of second openings, and with the progress of the dry etching, the plurality of holes are connected with each other at least at their upper parts including their open ends to form the second hole having an opening area larger than an opening area of the first hole.
    Type: Application
    Filed: September 15, 2011
    Publication date: August 23, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenichi IDE
  • Publication number: 20100180655
    Abstract: The present disclosure relates to a hot rolling apparatus for manufacturing a metal plate by hot-rolling-treating a metal material including copper.
    Type: Application
    Filed: June 18, 2008
    Publication date: July 22, 2010
    Inventors: Kengo Ishige, Yasuo Matsunaga, Hiroyuki Otsuka, Kenichi Ide, Masahiro Kuchi, Hisashi Honjou
  • Publication number: 20070291955
    Abstract: According to one embodiment, to provide a sound reproducing apparatus comprising a storage unit which stores content information therein, a communication unit which transmits the content information stored in the storage unit to an external device through wireless communication, a reproducing unit which reproduces the content information according to a set sound volume, an operation unit which outputs an operation signal for setting a reproducing sound volume, and a control unit which changes the set sound volume of the reproducing unit in response to the operation signal from the operation unit or sound volume information received by the communication unit, and which transmits sound volume information according to the set sound volume from the communication unit to the external device.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 20, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Yamashita, Kenichi Ide
  • Publication number: 20070146315
    Abstract: According to one embodiment, a key input device and a key input method thereof are disclosed. A key input device 1 is provided which sets a plurality of meanings by the operation with one input key. There are provided both or one of a guard section Gk after a judgment section Hk for selecting the meaning where the meaning corresponding to the preceding judgment section Hk is output by a setting operation for performing the selection, and a subsequent cancel section Ck where the transition procedure of the judgment sections Hk can be canceled halfway. The setting of undesired information is avoided even if there is caused a delay in the setting operation. The setting operation of the plurality of judgment sections Hk transiting in a time-series manner can be canceled in the middle of the transition.
    Type: Application
    Filed: December 26, 2006
    Publication date: June 28, 2007
    Inventor: Kenichi Ide
  • Patent number: 7137283
    Abstract: A material 1 to be shaped is reduced and formed by bringing dies with convex forming surfaces, when viewed from the side of the transfer line of the material 1, close to the transfer line from above and below the material 1, in synchronism with each other, while giving the dies a swinging motion in such a manner that the portions of the forming surfaces of the dies, in contact with the material 1, are transferred from the upstream to the downstream side in the direction of the transfer line.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: November 21, 2006
    Assignees: Ishikawajima-Harima Heavy Industries Co., Ltd., NKK Corporation
    Inventors: Shigeki Narushima, Kenichi Ide, Yasushi Dodo
  • Publication number: 20060116174
    Abstract: A mobile telephone device includes a communication part configured to perform wireless communication with an external mobile telephone device M, a talking part configured to make a call to the external mobile telephone device by modulating a voice signal from a vocoder, transmitting it from the communication part, demodulating the voice signal received by the communication part, and reproducing it by a speaker, a display part configured to display an image, and a control part configured to display information related to an operational mode of the mobile telephone device of a sender together with an incoming notice if there is this information among the communication information of which incoming is detected by the communication part and to control the mobile telephone device so as to wait for an operation for talking.
    Type: Application
    Filed: November 30, 2005
    Publication date: June 1, 2006
    Inventor: Kenichi Ide