Patents by Inventor Kenichi Imura
Kenichi Imura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7803660Abstract: In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.Type: GrantFiled: December 9, 2008Date of Patent: September 28, 2010Assignee: Renesas Electronics CorporationInventors: Fumio Murakami, Kenichi Imura, Makoto Araki
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Publication number: 20090093087Abstract: In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.Type: ApplicationFiled: December 9, 2008Publication date: April 9, 2009Inventors: Fumio MURAKAMI, Kenichi Imura, Makoto Araki
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Patent number: 7467464Abstract: A method for manufacturing a multi media card comprises the steps of: providing a substrate, mounting a first flash memory chip and a controller chip for controlling the flash memory chip over a front surface of the substrate, molding the first flash memory chip and the controller chip by a resin, providing a case having a main surface and a back surface, wherein the back surface of the case has a first recess and a second recess, and, covering the resin and the front surface of the substrate by the case. The depth of the first recess is deeper than the depth of the second recess. The resin is fitted in the first recess. An edge portion of the substrate is fitted in the second recess. The substrate warps so that a central portion of the substrate projects in a direction away from the case.Type: GrantFiled: December 3, 2007Date of Patent: December 23, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems, Co., Ltd.Inventors: Takahiro Osawa, Yoichi Kawata, Atsushi Fujishima, Tamaki Wada, Kenichi Imura
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Patent number: 7465609Abstract: In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.Type: GrantFiled: August 30, 2005Date of Patent: December 16, 2008Assignee: Renesas Technology Corp.Inventors: Fumio Murakami, Kenichi Imura, Makoto Araki
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Publication number: 20080164902Abstract: Provided is an inspection device which inspects a thin film transistor (TFT) for supplying a current to a light emitting element. The inspection device includes: a first current supply circuit which supplies a drain current between a drain and a source of the TFT; a gate voltage adjustment circuit which adjust a gate voltage to be applied to a gate of the TFT so as to allow a predetermined specified current to flow between the drain and source of the TFT; and a measurement unit which measures the gate voltage adjusted by the gate voltage adjustment circuit.Type: ApplicationFiled: July 9, 2007Publication date: July 10, 2008Inventors: Yoshitami Sakaguchi, Daiju Nakanao, Kenichi Imura, Yoshinori Mekata, Tomoyuki Taguchi
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Publication number: 20080115352Abstract: A memory card wherein a substrate is affixed to a cap is formed without the projection of substrate edges from a back surface of the cap. The memory card includes a substrate having a sealing member bonded to a recess in the cap. By utilizing a difference in thermal expansion coefficient between the sealing member and the substrate, the substrate is warped so that its central portion projects away from the cap. The shallow recess is deeper than the sum of the thickness of the substrate and the thickness of an adhesive for bonding the substrate to the bottom of the shallow recess, whereby peripheral edges of the substrate retract into the shallow recess without projecting from the back surface of the cap. The cap is shaped as a card several millimeters thick. A memory chip and control chip are incorporated in the sealing member.Type: ApplicationFiled: December 3, 2007Publication date: May 22, 2008Inventors: Takahiro Osawa, Yoichi Kawata, Atsushi Fujishima, Tamaki Wada, Kenichi Imura
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Patent number: 7322531Abstract: A memory card wherein a substrate is affixed to a cap is formed without the projection of substrate edges from a back surface of the cap. The memory card includes a substrate having a sealing member bonded to a recess in the cap. By utilizing a difference in thermal expansion coefficient between the sealing member and the substrate, the substrate is warped so that its central portion projects away from the cap. The shallow recess is deeper than the sum of the thickness of the substrate and the thickness of an adhesive for bonding the substrate to the bottom of the shallow recess, whereby peripheral edges of the substrate retract into the shallow recess without projecting from the back surface of the cap. The cap is shaped as a card several millimeters thick. A memory chip and control chip are incorporated in the sealing member.Type: GrantFiled: January 6, 2006Date of Patent: January 29, 2008Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Technology CorporationInventors: Takahiro Osawa, Yoichi Kawata, Atsushi Fujishima, Tamaki Wada, Kenichi Imura
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Patent number: 7295030Abstract: To test electrical characteristics of a Thin Film Transistor (TFT) with a source or drain terminal left open and exposed, using a non-contact current source and protecting the TFTs from adverse effects, such as contamination, destruction, and the like. A tester 100 is provided to test a TFT array substrate 14, the tester including ion flow supply devices 16 and 18 for supplying an ion flow onto the surface of a substrate 14. Thereon, an array 12 of TFTs is formed, each TFT being connected to an electrode having a source or a drain left open and exposed; a control circuit 24 for supplying an operating voltage to a gate electrode of the TFT to be tested in the array; and a measurement circuit 24 for measuring an operating current via the testing TFT source or drain that remain in a non open state.Type: GrantFiled: November 7, 2005Date of Patent: November 13, 2007Assignee: International Business Machines CorporationInventors: Kenichi Imura, Daiju Nakano, Yoshitami Sakaguchi
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Patent number: 7282943Abstract: Provided is an inspection device which inspects a thin film transistor (TFT) for supplying a current to a light emitting element. The inspection device includes: a first current supply circuit which supplies a drain current between a drain and a source of the TFT; a gate voltage adjustment circuit which adjust a gate voltage to be applied to a gate of the TFT so as to allow a predetermined specified current to flow between the drain and source of the TFT; and a measurement unit which measures the gate voltage adjusted by the gate voltage adjustment circuit.Type: GrantFiled: October 21, 2004Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Yoshitami Sakaguchi, Daiju Nakanao, Kenichi Imura, Yoshinori Mekata, Tomoyuki Taguchi
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Patent number: 7144755Abstract: At the time of performing resin molding for a matrix frame in the fabrication of semiconductor integrated circuit devices, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, so as to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities, while the pressure therein is regulated in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of the product being obtained.Type: GrantFiled: August 19, 2004Date of Patent: December 5, 2006Assignees: Renesas Technology Corp., Eastern Japan Semiconductor Technologies, Inc.Inventors: Bunshi Kuratomi, Fukumi Shimizu, Kenichi Imura, Katsushige Namiki, Fumio Murakami
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Patent number: 7086600Abstract: A memory card wherein a substrate is affixed to a cap is formed without the projection of substrate edges from a back surface of the cap. The memory card includes a substrate having a sealing member bonded to a recess in the cap. By utilizing a difference in thermal expansion coefficient between the sealing member and the substrate, the substrate is warped so that its central portion projects away from the cap. The shallow recess is deeper than the sum of the thickness of the substrate and the thickness of an adhesive for bonding the substrate to the bottom of the shallow recess, whereby peripheral edges of the substrate retract into the shallow recess without projecting from the back surface of the cap. The cap is shaped as a card several millimeters thick. A memory chip and control chip are incorporated in the sealing member.Type: GrantFiled: February 2, 2001Date of Patent: August 8, 2006Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Takahiro Osawa, Yoichi Kawata, Atsushi Fujishima, Tamaki Wada, Kenichi Imura
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Publication number: 20060108430Abstract: A memory card wherein a substrate is affixed to a cap is formed without the projection of substrate edges from a back surface of the cap. The memory card includes a substrate having a sealing member bonded to a recess in the cap. By utilizing a difference in thermal expansion coefficient between the sealing member and the substrate, the substrate is warped so that its central portion projects away from the cap. The shallow recess is deeper than the sum of the thickness of the substrate and the thickness of an adhesive for bonding the substrate to the bottom of the shallow recess, whereby peripheral edges of the substrate retract into the shallow recess without projecting from the back surface of the cap. The cap is shaped as a card several millimeters thick. A memory chip and control chip are incorporated in the sealing member.Type: ApplicationFiled: January 6, 2006Publication date: May 25, 2006Inventors: Takahiro Osawa, Yoichi Kawata, Atsushi Fujishima, Tamaki Wada, Kenichi Imura
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Publication number: 20060097745Abstract: To test electrical characteristics of a Thin Film Transistor (TFT) with a source or drain terminal left open and exposed, using a non-contact current source and protecting the TFTs from adverse effects, such as contamination, destruction, and the like. A tester 100 is provided to test a TFT array substrate 14, the tester including ion flow supply devices 16 and 18 for supplying an ion flow onto the surface of a substrate 14. Thereon, an array 12 of TFTs is formed, each TFT being connected to an electrode having a source or a drain left open and exposed; a control circuit 24 for supplying an operating voltage to a gate electrode of the TFT to be tested in the array; and a measurement circuit 24 for measuring an operating current via the testing TFT source or drain that remain in a non open state.Type: ApplicationFiled: November 7, 2005Publication date: May 11, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kenichi Imura, Daiju Nakano, Yoshitami Sakaguchi
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Patent number: 7015069Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.Type: GrantFiled: February 2, 2005Date of Patent: March 21, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Yonezawa Electronics Co., Ltd.Inventors: Noriyuki Takahashi, Masayuki Suzuki, Kouji Tsuchiya, Takao Matsuura, Takanori Hashizume, Masahiro Ichitani, Kazunari Suzuki, Takafumi Nishita, Kenichi Imura, Takashi Miwa
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Publication number: 20060046340Abstract: In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.Type: ApplicationFiled: August 30, 2005Publication date: March 2, 2006Inventors: Fumio Murakami, Kenichi Imura, Makoto Araki
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Publication number: 20050127535Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.Type: ApplicationFiled: February 2, 2005Publication date: June 16, 2005Inventors: Noriyuki Takahashi, Masayuki Suzuki, Kouji Tsuchiya, Takao Matsuura, Takanori Hashizume, Masahiro Ichitani, Kazunari Suzuki, Takafumi Nishita, Kenichi Imura, Takashi Miwa
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Publication number: 20050104614Abstract: Provided is an inspection device which inspects a thin film transistor (TFT) for supplying a current to a light emitting element. The inspection device includes: a first current supply circuit which supplies a drain current between a drain and a source of the TFT; a gate voltage adjustment circuit which adjust a gate voltage to be applied to a gate of the TFT so as to allow a predetermined specified current to flow between the drain and source of the TFT; and a measurement unit which measures the gate voltage adjusted by the gate voltage adjustment circuit.Type: ApplicationFiled: October 21, 2004Publication date: May 19, 2005Applicant: International Business Machines CorporationInventors: Yoshitami Sakaguchi, Daiju Nakanao, Kenichi Imura, Yoshinori Mekata, Tomoyuki Taguchi
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Patent number: 6872597Abstract: The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.Type: GrantFiled: February 24, 2004Date of Patent: March 29, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Yonezawa Electronics Co., Ltd.Inventors: Noriyuki Takahashi, Masayuki Suzuki, Kouji Tsuchiya, Takao Matsuura, Takanori Hashizume, Masahiro Ichitani, Kazunari Suzuki, Takafumi Nishita, Kenichi Imura, Takashi Miwa
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Publication number: 20050019979Abstract: At the time of performing resin molding for a matrix frame in the fabrication of semiconductor integrated circuit devices, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, so as to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities, while the pressure therein is regulated in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of the product being obtained.Type: ApplicationFiled: August 19, 2004Publication date: January 27, 2005Inventors: Bunshi Kuratomi, Fukumi Shimizu, Kenichi Imura, Katsushige Namiki, Fumio Murakami
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Patent number: 6797542Abstract: At the time of performing resin molding for a matrix frame in the fabrication of semiconductor integrated circuit devices, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, so as to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities, while the pressure therein is regulated in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of the product being obtained.Type: GrantFiled: February 12, 2003Date of Patent: September 28, 2004Assignees: Renesas Technology Corp., Eastern Japan Semiconductor Technologies, Inc.Inventors: Bunshi Kuratomi, Fukumi Shimizu, Kenichi Imura, Katsushige Namiki, Fumio Murakami