Patents by Inventor Kenichi Ishikawa

Kenichi Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250096217
    Abstract: A method of manufacturing a semiconductor composite device includes picking up a composite integrated film from a formation substrate having a formation surface, the composite integrated film being in advance formed on the formation substrate; and bonding in a first bonding process the composite integrated film to a substrate front surface of a circuit board. The composite integrated film includes a base member thin film having a base member first surface and a base member second surface facing each other, one or more penetration parts each penetrating the base member thin film, one or more electrodes each including an electrode surface in a planar shape formed on the base member second surface's side, and an element disposed on the base member first surface. In the first bonding process, the base member second surface of the composite integrated film is bonded to the substrate front surface.
    Type: Application
    Filed: December 4, 2024
    Publication date: March 20, 2025
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Takuma ISHIKAWA, Takahito SUZUKI, Kenichi TANIGAWA, Hironori FURUTA, Toru KOSAKA, Yusuke NAKAI, Shinya JYUMONJI, Genichiro MATSUO, Chihiro TAKAHASHI, Hiroto KAWADA, Yuuki SHINOHARA
  • Publication number: 20250096330
    Abstract: In the electrode laminate of the present disclosure, a fixing member including a curable resin is disposed on at least one side face portion. The fixing member has a thin film region and a thick film region. The thin film region is formed on at least one end portion including the terminal end of the fixing member, and the thick film region is formed at a portion other than the thin film region. The thickness of the fixing member is thinnest at the terminal end. Further, the battery of the present disclosure includes the electrode laminate of the present disclosure and a laminate film sealing the electrode laminate.
    Type: Application
    Filed: May 20, 2024
    Publication date: March 20, 2025
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroshi NAGASE, Kenichi KAKISHITA, Shinya ISHIKAWA, Ryo KAGAMI, Norihiro OSE
  • Publication number: 20250087368
    Abstract: An image processing apparatus includes at least one memory configured to store instructions, and at least one processor configured to execute the instructions to process an image of a target region, and thereby compute a proximity index being an index relating to a proximity state of a plurality of persons captured in the image, and cause a predetermined apparatus to execute predetermined control, when the proximity index satisfies a criterion.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Applicant: NEC Corporation
    Inventors: Gaku NAKANO, Shoji NISHIMURA, Yoshitaka HIGETA, Youtarou NODA, Shigeki SHINODA, Yuzo SENDA, Shin TOMINAGA, Masumi ISHIKAWA, Daisuke IKEFUJI, Kana TAKIZAWA, Kenichi ISHII, Yoshiyuki SATOU, Eishi ARITA, Shota YAMAMOTO, Shinya YAMASAKI, Narumitsu NOTOMI, Aki NAKAMURA
  • Patent number: 12216397
    Abstract: A reflective mask blank for EUV lithography includes: a substrate; a multilayer reflective film for reflecting EUV light; and a phase shift film for shifting a phase of EUV light, the multilayer reflective film and the phase shift film formed on or above the substrate in this order. The phase shift film includes a layer 1 including ruthenium (Ru) and at least one selected from the group consisting of oxygen (O) and nitrogen (N). Among diffraction peaks derived from the phase shift film observed at 2?: from 20° to 50° by out-of-plane XRD method, a peak having the highest intensity has a half value width FWHM of 1.0° or more.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: February 4, 2025
    Assignee: AGC Inc.
    Inventors: Daijiro Akagi, Hirotomo Kawahara, Toshiyuki Uno, Ichiro Ishikawa, Kenichi Sasaki
  • Patent number: 12204240
    Abstract: A reflective mask blank includes a substrate; a multilayer reflective film that reflects EUV light; a protection film that protects the multilayer reflective film; and a phase shift film that shifts a phase of the EUV light, the substrate, the multilayer reflective film, the protection film, and the phase shift film being arranged in this order. The phase shift film contains at least one first element X1 selected from the first group consisting of ruthenium (Ru), iridium (Ir), platinum (Pt), palladium (Pd), and gold (Au), and at least one second element X2 selected from the second group consisting of oxygen (O), boron (B), carbon (C), and nitrogen (N). In the phase shift film, a chemical shift of a peak of 3d5/2 or a peak of 4f7/2 of the first element X1 observed by X-ray electron spectroscopy is less than 0.3 eV.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: January 21, 2025
    Assignee: AGC Inc.
    Inventors: Daijiro Akagi, Shunya Taki, Takuma Kato, Ichiro Ishikawa, Kenichi Sasaki
  • Publication number: 20230092233
    Abstract: An approach is provided in which the approach captures a set of individual indices corresponding to a set of psychological conditions of individual members of a team during a set of phases of a project. The approach computes, based on the set of individual indices, a set of team indices corresponding to the set of psychological conditions indicating a team state in each one of the set of phases of the project. The approach transmits a recommendation to a user in response to detecting a set of differences between the set of team indices and a set of expected values. The recommendation includes an action to increase the set of team indices.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 23, 2023
    Inventors: Katsuroh Hayashi, Kenichi Ishikawa, Takashi Okano
  • Patent number: 10464186
    Abstract: The method of the present invention comprises the steps of: previously obtaining correlation data between surface properties of the polishing pad dressed under a plurality of stages of dressing conditions and polishing effects of the work polished by the polishing pad dressed under the dressing conditions; determining an assumed dressing condition capable of achieving an object polishing effect from the correlation data; dressing the polishing pad under the assumed dressing condition determined; polishing the work; cleaning the polishing pad which has been used for polishing the work; and measuring a surface property of the cleaned polishing pad.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: November 5, 2019
    Assignees: FUJIKOSHI MACHINERY CORP., KANAZAWA INSTITUTE OF TECHNOLOGY
    Inventors: Kazutaka Shibuya, Jun Yanagisawa, Yoshio Nakamura, Michio Uneda, Kenichi Ishikawa
  • Patent number: 10449655
    Abstract: The polishing apparatus comprises: a dressing section for dressing a polishing pad; a measuring section for measuring a surface property of the polishing pad; a polishing result measuring section for measuring a polishing result of a work; a storing section for storing correlation data between dressing condition data for dressing the polishing pad, surface property of the polishing pad and polishing results, which are learned by an artificial intelligence; and an input section for inputting an object polishing result. The artificial intelligence performs a first arithmetic process, in which the surface property of the polishing pad corresponding to the object polishing result is inversely estimated on the basis of the correlation data, and a second arithmetic process, in which the corresponding dressing condition is derived on the basis of the surface property of the polishing pad inversely estimated.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: October 22, 2019
    Assignees: FUJIKOSHI MACHINERY CORP., KANAZAWA INSTITUTE OF TECHNOLOGY
    Inventors: Kazutaka Shibuya, Yoshio Nakamura, Michio Uneda, Kenichi Ishikawa
  • Publication number: 20180207768
    Abstract: The polishing apparatus comprises: a dressing section for dressing a polishing pad; a measuring section for measuring a surface property of the polishing pad; a polishing result measuring section for measuring a polishing result of a work; a storing section for storing correlation data between dressing condition data for dressing the polishing pad, surface property of the polishing pad and polishing results, which are learned by an artificial intelligence; and an input section for inputting an object polishing result. The artificial intelligence performs a first arithmetic process, in which the surface property of the polishing pad corresponding to the object polishing result is inversely estimated on the basis of the correlation data, and a second arithmetic process, in which the corresponding dressing condition is derived on the basis of the surface property of the polishing pad inversely estimated.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 26, 2018
    Inventors: Kazutaka SHIBUYA, Yoshio NAKAMURA, Michio UNEDA, Kenichi ISHIKAWA
  • Patent number: 10031241
    Abstract: A radiation dosimetry gel is excellent in heat resistance, and a radiation dosimeter includes the radiation dosimetry gel as a material for measuring a radiation dose. A radiation dosimetry gel includes a water-soluble organic polymer (A) having an organic acid salt structure or an organic acid anion structure, a silicate (B), and a dispersant (C) for the silicate, and a radiation dosimeter includes the radiation dosimetry gel as a material for measuring a radiation dose.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 24, 2018
    Assignees: RIKEN, NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Takuya Maeyama, Nobuhisa Fukunishi, Kenichi Ishikawa, Yasuhiro Ishida, Takuzo Aida, Kazuaki Fukasaku, Yoshihiro Kudo, Souichi Monma
  • Publication number: 20170350989
    Abstract: A radiation dosimetry gel is excellent in heat resistance, and a radiation dosimeter includes the radiation dosimetry gel as a material for measuring a radiation dose. A radiation dosimetry gel includes a water-soluble organic polymer (A) having an organic acid salt structure or an organic acid anion structure, a silicate (B), and a dispersant (C) for the silicate, and a radiation dosimeter includes the radiation dosimetry gel as a material for measuring a radiation dose.
    Type: Application
    Filed: December 18, 2015
    Publication date: December 7, 2017
    Applicants: RIKEN, NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Takuya MAEYAMA, Nobuhisa FUKUNISHI, Kenichi ISHIKAWA, Yasuhiro ISHIDA, Takuzo AIDA, Kazuaki FUKASAKU, Yoshihiro KUDO, Souichi MONMA
  • Publication number: 20170190018
    Abstract: The method of the present invention comprises the steps of: previously obtaining correlation data between surface properties of the polishing pad dressed under a plurality of stages of dressing conditions and polishing effects of the work polished by the polishing pad dressed under the dressing conditions; determining an assumed dressing condition capable of achieving an object polishing effect from the correlation data; dressing the polishing pad under the assumed dressing condition determined; polishing the work; cleaning the polishing pad which has been used for polishing the work; and measuring a surface property of the cleaned polishing pad.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 6, 2017
    Inventors: Kazutaka SHIBUYA, Jun YANAGISAWA, Yoshio NAKAMURA, Michio UNEDA, Kenichi ISHIKAWA
  • Patent number: 9630232
    Abstract: A punch constitutes, together with a die, a blanking die for punching a workpiece with a punching shape in which protrusions protrude outwards from an annular body. The punch includes a cylinder-shaped punch section and a holder section. In the punch section, a shape of the front end surface corresponding to the punching shape of the workpiece is continuous to a rear end surface, and includes a cutting edge on its front end surface. The holder section is a short cylinder including an inner circumferential surface formed in correspondence with an outer circumferential surface of the punch section to allow insertion of a rear part of the punch section. The protrusions are brought into intimate contact with the recesses of the holder section. A clearance is provided between a part of the punch section other than the protrusions and a part of the holder section other than the recesses.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: April 25, 2017
    Assignee: SHOWA PRECISION TOOLS CO., LTD.
    Inventors: Kenichi Ishikawa, Norimichi Ebisawa, Tomonari Hashiguchi
  • Publication number: 20160375479
    Abstract: A punch constitutes, together with a die, a blanking die for punching a workpiece with a punching shape in which protrusions protrude outwards from an annular body. The punch includes a cylinder-shaped punch section and a holder section. In the punch section, a shape of the front end surface corresponding to the punching shape of the workpiece is continuous to a rear end surface, and includes a cutting edge on its front end surface. The holder section is a short cylinder including an inner circumferential surface formed in correspondence with an outer circumferential surface of the punch section to allow insertion of a rear part of the punch section. The protrusions are brought into intimate contact with the recesses of the holder section. A clearance is provided between a part of the punch section other than the protrusions and a part of the holder section other than the recesses.
    Type: Application
    Filed: October 21, 2015
    Publication date: December 29, 2016
    Inventors: Kenichi Ishikawa, Norimichi Ebisawa, Tomonari Hashiguchi
  • Patent number: 9305891
    Abstract: A semiconductor integrated circuit is provided. In the semiconductor integrated circuit, each of ESD protection circuitries is disposed between two of TSV bumps arrayed in a matrix, the two being arranged adjacent to each other. First main power lines are disposed to overlap P-channel ESD protection elements. Second main power lines are disposed to overlap N-channel ESD protection elements. The first and second main power lines are arranged orthogonally to each other.
    Type: Grant
    Filed: February 7, 2015
    Date of Patent: April 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Kenichi Ishikawa
  • Patent number: 9213105
    Abstract: To measure three-dimensional dose distributions with a dosimeter, such as a gel dosimeter. In an embodiment of the present invention, provided is a gel dosimeter having water, as solvent or disperse medium, clay particles that swell with water, and recording material precursor, which are dissolved or dispersed with each other. The recording material precursor has an atom or ion, wherein the atom or ion changes its valence number by reacting with both of a radical and a molecular radical derivative. The radical is to be generated from the water ionized by irradiation of radiation rays, and the molecular radical derivative is a molecule to be formed by bonding the radicals with each other. By the time radiation rays are irradiated, the gel dosimeter has been free from a substance identical to the molecular radical derivative and has lost fluidity.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: December 15, 2015
    Assignee: RIKEN
    Inventors: Takuya Maeyama, Ryutaro Himeno, Shu Takagi, Nobuhisa Fukunishi, Shigeho Noda, Takuya Furuta, Kazuaki Fukasaku, Kenichi Ishikawa
  • Publication number: 20150145053
    Abstract: A semiconductor integrated circuit is provided. In the semiconductor integrated circuit, each of ESD protection circuitries is disposed between two of TSV bumps arrayed in a matrix, the two being arranged adjacent to each other. First main power lines are disposed to overlap P-channel ESD protection elements. Second main power lines are disposed to overlap N-channel ESD protection elements. The first and second main power lines are arranged orthogonally to each other.
    Type: Application
    Filed: February 7, 2015
    Publication date: May 28, 2015
    Inventor: Kenichi Ishikawa
  • Patent number: 8994110
    Abstract: A semiconductor integrated circuit is provided. In the semiconductor integrated circuit, each of ESD protection circuitries is disposed between two of TSV bumps arrayed in a matrix, the two being arranged adjacent to each other. First main power lines are disposed to overlap P-channel ESD protection elements. Second main power lines are disposed to overlap N-channel ESD protection elements. The first and second main power lines are arranged orthogonally to each other.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 31, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kenichi Ishikawa
  • Publication number: 20140295564
    Abstract: To measure three-dimensional dose distributions with a dosimeter, such as a gel dosimeter. In an embodiment of the present invention, provided is a gel dosimeter having water, as solvent or disperse medium, clay particles that swell with water, and recording material precursor, which are dissolved or dispersed with each other. The recording material precursor has an atom or ion, wherein the atom or ion changes its valence number by reacting with both of a radical and a molecular radical derivative. The radical is to be generated from the water ionized by irradiation of radiation rays, and the molecular radical derivative is a molecule to be formed by bonding the radicals with each other. By the time radiation rays are irradiated, the gel dosimeter has been free from a substance identical to the molecular radical derivative and has lost fluidity.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 2, 2014
    Applicant: RIKEN
    Inventors: Takuya MAEYAMA, Ryutaro HIMENO, Syu TAKAGI, Nobuhisa FUKUNISHI, Shigeho NODA, Takuya FURUTA, Kazuaki FUKASAKU, Kenichi ISHIKAWA
  • Publication number: 20140145266
    Abstract: A semiconductor integrated circuit is provided. In the semiconductor integrated circuit, each of ESD protection circuitries is disposed between two of TSV bumps arrayed in a matrix, the two being arranged adjacent to each other. First main power lines are disposed to overlap P-channel ESD protection elements. Second main power lines are disposed to overlap N-channel ESD protection elements. The first and second main power lines are arranged orthogonally to each other.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 29, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Kenichi Ishikawa