Abstract: An optical waveguide includes a diamond layer including a first surface, a second surface and a diamond layer including a complex defect; a first clad layer in contact with the first surface; a second clad layer in contact with the second surface and including a polarity; and a metal layer in Schottky contact with the second clad layer.

Abstract: The present disclosure relates to the treatment of cancer using a combination therapy comprising Compound 1 and/or tautomers thereof or a pharmaceutically acceptable salt or hydrate thereof, and a second therapy.

Abstract: Various implementations described herein relate to systems and methods for transferring data from a source device to a destination device including receiving, by the destination device, a copy request from a host, performing, by the destination device, transfer with the source device to transfer data from buffers of the source device to buffers of the destination device, and writing, by the destination device, the data to a non-volatile storage of the destination device.

Abstract: Various implementations described herein relate to systems and methods for providing data protection and recovery for drive failures, including receiving, by a controller of a first storage device, a request from the host. In response to receiving the request, the controller transfers new data from a second storage device. The controller determines an XOR result by performing an XOR operation of the new data and existing data, the existing data is stored in a non-volatile storage.

Abstract: The present invention relates to a method of predicting the likelihood that a patient will respond therapeutically to a pancreatic cancer treatment comprising the administration of 2-[(2S)-1-azabicyclo[2.2.2]oct-2-yl]-6-(3-methyl-1H-pyrazol-4-yl)thieno[3,2-d]pyrimidin-4(3H)-one (Compound 1) and/or tautomers thereof or a pharmaceutically acceptable salt or hydrate thereof, comprising the steps of: STEP (1): determining a KRAS gene mutation status of a sample from a patient, and STEP (2): predicting an increased likelihood that the patient will respond therapeutically to the pancreatic cancer treatment if the patient has the presence of KRAS gene mutation(s), and to methods of treating pancreatic cancer.

Abstract: The present disclosure relates to methods useful for determining whether to treat cancer in a patient, and treating cancer in a patient, by administering a therapeutically effective amount of Compound 1 and/or tautomers thereof or a pharmaceutically acceptable salt or hydrate thereof.

Abstract: According to one embodiment, a memory system includes a controller. The controller controls throttling to make a performance value of the memory system fall between a first performance value and a second performance value. The throttling limits the number of times of accesses per unit time to a nonvolatile memory. The first performance value is calculated based on a third performance value of the memory system and is greater than the third performance value. The third performance value is a value which is expected to be reached at a time when a first period has elapsed since the memory system started being used if throttling is not performed. The second performance value is provided between the first performance value and the third performance value.

Abstract: The present invention relates to a method of predicting the likelihood that a patient will respond therapeutically to a pancreatic cancer treatment comprising the administration of 2-[(2S)-1-azabicyclo[2.2.2]oct-2-yl]-6-(3-methyl-1H-pyrazol-4-yl)thieno[3,2-d]pyrimidin-4(3H)-one (Compound 1) and/or tautomers thereof or a pharmaceutically acceptable salt or hydrate thereof, comprising the steps of: STEP (1): determining a KRAS gene mutation status of a sample from a patient, and STEP (2): predicting an increased likelihood that the patient will respond therapeutically to the pancreatic cancer treatment if the patient has the presence of KRAS gene mutation(s), and to methods of treating pancreatic cancer.

Abstract: According to one embodiment, a memory system includes a controller. The controller controls throttling to make a performance value of the memory system fall between a first performance value and a second performance value. The throttling limits the number of times of accesses per unit time to a nonvolatile memory. The first performance value is calculated based on a third performance value of the memory system and is greater than the third performance value. The third performance value is a value which is expected to be reached at a time when a first period has elapsed since the memory system started being used if throttling is not performed. The second performance value is provided between the first performance value and the third performance value.

Abstract: According to one embodiment, a memory system includes a controller. The controller controls throttling to make a performance value of the memory system fall between a first performance value and a second performance value. The throttling limits the number of times of accesses per unit time to a nonvolatile memory. The first performance value is calculated based on a third performance value of the memory system and is greater than the third performance value. The third performance value is a value which is expected to be reached at a time when a first period has elapsed since the memory system started being used if throttling is not performed. The second performance value is provided between the first performance value and the third performance value.

Abstract: According to one embodiment, a memory system includes a controller. The controller controls throttling to make a performance value of the memory system fall between a first performance value and a second performance value. The throttling limits the number of times of accesses per unit time to a nonvolatile memory. The first performance value is calculated based on a third performance value of the memory system and is greater than the third performance value. The third performance value is a value which is expected to be reached at a time when a first period has elapsed since the memory system started being used if throttling is not performed. The second performance value is provided between the first performance value and the third performance value.

Abstract: A photoelectric conversion apparatus includes a plurality of elements (D) for receiving reflected light from an object, photoelectrically converting it into image signals (OS1-OS4), and outputting the image signals, a first output buffer (121) for outputting image signals received from even elements of the plurality of elements in the line from one end to the other end, a second output buffer (122) for outputting image signals received from odd elements from one end to the other end, a third output buffer (123) for outputting image signals received from even elements from the other end to the one end, and a fourth output buffer (124) for outputting image signals received from odd elements from the other end to the one end.

Abstract: According to an image reading apparatus of the present invention, a basic section CPU controls a scanning speed of a carriage of a scanner unit at a predetermined level by driving a scanning motor. A CCD of the scanner unit receives reflection light from a document scanned by the scanner unit, photoelectrically converts the reflection light into electric signals to accumulate it therein. An ASIC for controlling the scanner controls the processing of the electric signals accumulated in the CCD with a cyclic period corresponding to a magnification rate set for an image of the scanned document.

Abstract: An image processing apparatus processes an image signal obtained by subjecting optical image information to photoelectric conversion. An image fetch circuit converts the image signal into a digital signal and outputs it as input image data of one line. An image data processing circuit fetches the input image data of one line from the image fetch circuit in units of one pixel, and subjects it to predetermined image processing. A drive circuit at least supplies the image fetch circuit with a predetermined drive pulse signal which enables a high-speed operation of the image fetch circuit. A timing setting circuit programs, from the outside, timing of the drive pulse signal supplied from the drive circuit.