Patents by Inventor Kenichi Kadota

Kenichi Kadota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7062409
    Abstract: A method of detecting failure of manufacturing apparatuses has: identifying a low-yield-period apparatus having a significantly lower yield period compared with other manufacturing apparatus and the significantly lower yield period by comparing yields of a plurality of manufacturing apparatuses used in parallel in a specific manufacturing process for each time period when the manufacturing apparatuses were used; identifying a downward-tendency apparatus having a significant downward tendency in yield compared with the other manufacturing apparatus by comparing recent yield trends of the plurality of manufacturing apparatuses; and issuing multi-level warnings to the low-yield-period apparatus and the downward-tendency apparatus.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: June 13, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Kadota
  • Patent number: 7043384
    Abstract: A failure detection system includes a wafer test information input unit which acquires pass/fail maps for wafers for a plurality of types of semiconductor devices, displaying failure chip areas based on results of electrical tests performed on chips; an analogous test information input unit which classifies the electrical tests into analogous electrical tests with regard to analogous failures among the semiconductor devices; a subarea setting unit which assigns subareas common to the types of semiconductor devices on a wafer surface; a characteristic quantity calculation unit which statistically calculates characteristic quantities based on a number of the failure chip areas included in the subareas for each analogous electrical test; and a categorization unit which obtains correlation coefficients between the characteristic quantities corresponding to the subareas, and classifies clustering failure patterns of the failure chip areas into categories by comparing the correlation coefficients with a threshold.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: May 9, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Matsushita, Kenichi Kadota, Yoshiyuki Shioyama
  • Patent number: 6975953
    Abstract: An analysis method for a semiconductor device includes measuring electrical characteristics of TEGs fabricated on a semiconductor substrate; classifying the TEGs into a first TEG category where a systematic failure has not occurred and a second TEG category where the systematic failure has occurred based on the electrical characteristics; creating a first comparison Mahalanobis reference space using first parameters of the TEGs in the first TEG category from among parameters of the TEGs expressed as numerical values; calculating a first comparison Mahalanobis distance of the first parameters and a second comparison Mahalanobis distance of second parameters of the TEGs in the second TEG category by using the first comparison Mahalanobis reference space; and comparing the first and second comparison Mahalanobis distances.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: December 13, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Kadota
  • Publication number: 20050251365
    Abstract: A system for identifying a manufacturing tool causing a failure, includes a data generating module generating factorial effect data, based on information on a failure lot group by using an orthogonal array, a chart generating module generating a factorial effect chart based on the factorial effect data, a selection module selecting failure lots caused by the same reason for a failure from among the failure lot group, based on the factorial effect chart, and an identification module identifying a manufacturing tool used as a common tool for the selected plurality of failure lots, based on history information of the manufacturing tool group.
    Type: Application
    Filed: March 28, 2005
    Publication date: November 10, 2005
    Inventors: Hiroshi Matsushita, Kenichi Kadota
  • Publication number: 20050194590
    Abstract: A control system for a manufacturing apparatus includes manufacturing information input unit acquiring time series data of apparatus parameters controlling manufacturing apparatuses; failure pattern classification module classifying in-plane distributions of failures of each of the wafers into failure patterns; an index calculation unit configured to statistically process the time series data by algorithms to calculate indices corresponding to the respective algorithms; an index analysis unit providing first and second frequency distributions of the indices categorized with and without the target failure pattern, to implement significance test between the first and second frequency distributions; and an abnormal parameter extraction unit extracting failure cause index of failure pattern by comparing value of the significance test with test reference value.
    Type: Application
    Filed: March 2, 2005
    Publication date: September 8, 2005
    Inventors: Hiroshi Matsushita, Tomonobu Noda, Kenichi Kadota, Junji Sugamoto, Yukihiro Ushiku
  • Patent number: 6916507
    Abstract: An aqueous water repellent useful in the treatment of substrates of lignocellulose-origin materials or the like is characterized by comprising the product of co-hydrolytic condensation of (A) 100 parts by weight of an organosilicon compound having the formula: (R1)a(OR2)bSiO(4-a-b)/2??(1) wherein R1 is alkyl, R2 is alkyl, 0.75?a?1.5, 0.2?b?3 and 0.9<a+b?4, and (B) 0.5-49 parts by weight of an amino-containing alkoxysilane having the formula: R3R4NR5—SiR6n(OR2)3-n??(2) wherein R3 and R4 are H or alkyl or aminoalkyl, R5 is a divalent hydrocarbon group, R6 is alkyl, and n is 0 or 1, or a partial hydrolyzate thereof in the presence of an organic acid or inorganic acid.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: July 12, 2005
    Assignees: Shin-Etsu Chemical Co., Ltd., Sumitomo Forestry Co., Ltd.
    Inventors: Kazuyuki Matsumura, Akira Yamamoto, Hisayoshi Suda, Kenichi Kadota
  • Publication number: 20050102591
    Abstract: A failure detection system includes a wafer test information input unit which acquires pass/fail maps for wafers for a plurality of types of semiconductor devices, displaying failure chip areas based on results of electrical tests performed on chips; an analogous test information input unit which classifies the electrical tests into analogous electrical tests with regard to analogous failures among the semiconductor devices; a subarea setting unit which assigns subareas common to the types of semiconductor devices on a wafer surface; a characteristic quantity calculation unit which statistically calculates characteristic quantities based on a number of the failure chip areas included in the subareas for each analogous electrical test; and a categorization unit which obtains correlation coefficients between the characteristic quantities corresponding to the subareas, and classifies clustering failure patterns of the failure chip areas into categories by comparing the correlation coefficients with a threshold.
    Type: Application
    Filed: February 24, 2004
    Publication date: May 12, 2005
    Inventors: Hiroshi Matsushita, Kenichi Kadota, Yoshiyuki Shioyama
  • Publication number: 20050021303
    Abstract: A method of detecting a wafer failure includes extracting the wafer ID of a target wafer in the target lot from the lot ID, extracting the location information of a failure in the target wafer, calculating a to-be-quantified first wafer feature amount for unevenness of a wafer failure distribution, calculating a first lot feature amount for each target lot, extracting a fabrication process for the target lot and a fabrication apparatus, carrying out a significant test for the fabrication apparatus used in each fabrication process, and detecting the fabrication apparatus with a significant difference as a first abnormal apparatus.
    Type: Application
    Filed: June 14, 2004
    Publication date: January 27, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Matsushita, Kenichi Kadota
  • Publication number: 20050021299
    Abstract: A method of detecting failure of manufacturing apparatuses has: identifying a low-yield-period apparatus having a significantly lower yield period compared with other manufacturing apparatus and the significantly lower yield period by comparing yields of a plurality of manufacturing apparatuses used in parallel in a specific manufacturing process for each time period when the manufacturing apparatuses were used; identifying a downward-tendency apparatus having a significant downward tendency in yield compared with the other manufacturing apparatus by comparing recent yield trends of the plurality of manufacturing apparatuses; and issuing multi-level warnings to the low-yield-period apparatus and the downward-tendency apparatus.
    Type: Application
    Filed: September 26, 2003
    Publication date: January 27, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenichi Kadota
  • Publication number: 20040255198
    Abstract: A failure analysis method according to the invention includes inputting the positions of failures in multiple wafers of an input device; preparing multiple sections in the multiple wafers; calculating feature amounts, which are represented by at least one numerical value representing a distribution of the failures in the multiple wafers, for each of the multiple sections; and representing by a first numerical value, the degree of similarity between the multiple wafers in terms of the feature amounts. Subsequently, the method includes detecting another wafer, which has the first numerical value greater than a predetermined first threshold, for each of the multiple wafers and forming a similar wafer group of multiple wafers with similar distributions of the failures.
    Type: Application
    Filed: March 17, 2004
    Publication date: December 16, 2004
    Inventors: Hiroshi Matsushita, Kenichi Kadota, Kenji Kawabata, Yoshiyuki Shioyama
  • Publication number: 20040228186
    Abstract: An analysis method for a semiconductor device includes measuring electrical characteristics of TEGs fabricated on a semiconductor substrate; classifying the TEGs into a first TEG category where a systematic failure has not occurred and a second TEG category where the systematic failure has occurred based on the electrical characteristics; creating a first comparison Mahalanobis reference space using first parameters of the TEGs in the first TEG category from among parameters of the TEGs expressed as numerical values; calculating a first comparison Mahalanobis distance of the first parameters and a second comparison Mahalanobis distance of second parameters of the TEGs in the second TEG category by using the first comparison Mahalanobis reference space; and comparing the first and second comparison Mahalanobis distances.
    Type: Application
    Filed: February 25, 2004
    Publication date: November 18, 2004
    Inventor: Kenichi Kadota
  • Publication number: 20040113117
    Abstract: An aqueous water repellent useful in the treatment of substrates of lignocellulose-origin materials or the like is characterized by comprising the product of co-hydrolytic condensation of (A) 100 parts by weight of an organosilicon compound having the formula:
    Type: Application
    Filed: September 30, 2003
    Publication date: June 17, 2004
    Inventors: Kazuyuki Matsumura, Akira Yamamoto, Hisayoshi Suda, Kenichi Kadota