Abstract: In a method of forming a gate conductor layer which surrounds a semiconductor pillar, a first impurity region and a first mask material layer having oxidation resistance are respectively formed in a top part of a semiconductor pillar and on a side wall of the semiconductor pillar, thermal or chemical oxidation is performed on the entire stack, a first insulation layer is formed on the exposed surface of the first impurity region, the first mask material layer is removed, and a gate conductor layer is formed in an upper part of the first insulation layer.

Abstract: P+ layers which entirely cover top parts of Si pillars and which surround the Si pillars at equal widths in a plan view are formed by self-alignment with the Si pillars, W layers are formed on the P+ layers, a band-shaped contact hole which is in contact with respective partial regions of the W layers and which extends in the Y direction is formed, and a supply wiring metal layer is formed by filling the band-shaped contact hole. The partial regions of the W layers are shaped so as to protrude to outside of the band-shaped contact hole in a plan view.

Abstract: A method for forming a first impurity region 3 connected to lower portions of first semiconductor pillars and second impurity regions 4a and 4b connected to lower portions of second semiconductor pillars includes forming a semiconductor layer 100 having an impurity concentration lower than an impurity concentration of each of the first impurity region 3 and the second impurity regions 4a and 4b in impurity boundary regions of the first impurity region 3 and the second impurity regions 4a and 4b in a vertical direction and a horizontal direction.

Abstract: There is provided a storage water of a silicon wafer wherein a liquid temperature of the storage water is 0 to 18° C. And there is provided a shower water of a silicon wafer wherein a liquid temperature of the shower water is 0 to 18° C. The wafer is stored in the storage water, and showered using the shower water. The present invention also relates to a method for storing silicon wafer wherein the silicon wafer is showered using a shower water of which liquid temperature is 0 to 18° C., and is then stored in liquid using a storage water of which liquid temperature is 0 to 18° C. Thereby, there can be provided a water for storing a silicon wafer, a method for storing it, a water for showering it and a method for showering it wherein degradation of the wafer quality can be prevented.

Abstract: An exposure apparatus for exposing a substrate to light via an original plate. A projection optical system projects a pattern of the original plate onto the substrate, a liquid immersion mechanism generates a liquid immersion state in which a gap between the final surface of the projection optical system and the substrate is filled with liquid, a first photosensor detects light which has passed through the projection optical system, a second photosensor, different from the first photosensor, detects light that has passed through the projection optical system, and a controller calibrates an output from the first photosensor in the liquid immersion state based on a first output from the first photosensor in the liquid immersion state, a second output from the first photosensor in a non-liquid immersion state, and a third output from a reference illuminometer.

Abstract: An exposure apparatus for exposing a substrate to light via an original plate includes a projection optical system configured to project a pattern of the original plate onto the substrate, a liquid immersion mechanism configured to generate a liquid immersion state in which the gap between the projection optical system and the substrate is filled with liquid, a first photosensor configured to detect light which has passed through the projection optical system, and a controller configured to calibrate an output from the first photosensor in the liquid immersion state based on a first output from the first photosensor in the liquid immersion state, a second output from the first photosensor in a non liquid immersion state, and a third output from a reference illuminometer for detecting light which has passed through the projection optical system in the non liquid immersion state.

Abstract: There is provided a storage water of a silicon wafer wherein a liquid temperature of the storage water is 0 to 18° C. And there is provided a shower water of a silicon wafer wherein a liquid temperature of the shower water is 0 to 18° C. The wafer is stored in the storage water, and showered using the shower water. The present invention also relates to a method for storing silicon wafer wherein the silicon wafer is showered using a shower water of which liquid temperature is 0 to 18° C., and is then stored in liquid using a storage water of which liquid temperature is 0 to 18° C. Thereby, there can be provided a water for storing a silicon wafer, a method for storing it, a water for showering it and a method for showering it wherein degradation of the wafer quality can be prevented.

Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.

Abstract: After an SAC film is formed to a thickness not to fill the spaces between gate electrodes in a memory cell region, a silicon oxide film is formed to a thickness to fill the spaces. A side wall made of a silicon oxide film is formed on the side surface of only a gate electrode in a peripheral circuit region, and a metal silicide is formed on the exposed substrate surface. A BLC film is formed on the entire surface. A contact hole is formed in self alignment using the SAC film and the BLC film. In this method, silicidation of the source/drain of a transistor in the peripheral circuit region and the self-alignment technique such as BLC or SAC can be simultaneously used to enable an increase in the degree of integration and improvement of performance of a semiconductor device having a metal silicide on the transistor in the logic circuit.

Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.

Abstract: A terminal base (N1) is electrically connected to a conductive foil pattern (201), and a terminal base (N2) is electrically connected to switching elements (T1, T2, T3). The control electrodes of the switching elements (T1, T2, T3) are electrically connected to resistors (R10, R20, R30) with wire lines (WL). Thus, by using the resistors on which the wire lines can be bonded direct, a size-reduced semiconductor device is provided.

Abstract: An FM communication device employs a logarithmic amplifier which performs logarithmic conversion of a frequency modulated signal. The beat component level of the output signal of the logarithmic amplifier is checked with a reference level for detecting interference. With the construction set forth above, the FM communication device, according to the invention, detects the ripple of the received FM signal caused by interference of another FM signal by means of the logarithmic amplifier which converts the received FM signal logarithmically and the detection circuit which AM-detects the output signal of the logarithmic amplifier, so that the interference can be detected via the output signal of the detection circuit. In the preferred construction set forth above, the logarithmic amplifier which is often utilized in a detection system for reception magnitude is sufficient as an amplifier circuit required for detecting the interference, and no high-gain and high-performance amplifier is required.

Abstract: A control circuit uses an adjustable resistance to generate a first control signal whose amplitude varies with the setting of the resistance and a second, step-like control signal whose level changes from a first to a second level at a predetermined setting of the resistance. The variable resistance is coupled to the collector of one of a pair of transistors whose emitters are commonly connected to a reference potential. The adjustable resistance's tap, which provides the first control signal, is connected to the base of the one transistor. A collector impedance and the variable resistance are coupled between the collector circuit of the one transistor and a voltage source. An output of the impedance is connected to the base of the other transistor, whose collector provides the second control signal.

Abstract: A controllable rectifier circuit which may be used in a power supply selectively produces a half-wave or a full-wave rectified signal. The rectifier circuit includes a pair of input terminals for receiving an AC signal and a bridge rectifier coupled to the input terminals and including a pair of output terminals across which a rectified AC signal is produced. The bridge rectifier comprises a first current path including a switchable rectifier for conducting positive half cycles of the AC signal and a second current path including a switchable rectifier for conducting negative half cycles of the AC signal. A pulse generator is supplied with reduced amplitude versions of the positive and negative half cycles of the AC signal, in sequence, to produce an output pulse when the reduced amplitude of the half cycle supplied thereto is less than a predetermined level.