Patents by Inventor Kenichi Kanazawa

Kenichi Kanazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10711372
    Abstract: A silicon carbide epitaxial wafer manufacturing method includes: a stabilization step of nitriding, oxidizing or oxynitriding and stabilizing silicon carbide attached to an inner wall surface of a growth furnace; after the stabilization step, a bringing step of bringing a substrate in the growth furnace; and after the bringing step, a growth step of epitaxially growing a silicon carbide epitaxial layer on the substrate by supplying a process gas into the growth furnace to manufacture a silicon carbide epitaxial wafer.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 14, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihito Ohno, Kenichi Hamano, Takashi Kanazawa
  • Patent number: 10707075
    Abstract: A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: July 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Hamano, Akihito Ohno, Takuma Mizobe, Masashi Sakai, Yasuhiro Kimura, Yoichiro Mitani, Takashi Kanazawa
  • Publication number: 20200144053
    Abstract: A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 7, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenichi HAMANO, Akihito OHNO, Takuma MIZOBE, Masashi SAKAI, Yasuhiro KIMURA, Yoichiro MITANI, Takashi KANAZAWA
  • Publication number: 20190284718
    Abstract: A silicon carbide epitaxial wafer manufacturing method includes: a stabilization step of nitriding, oxidizing or oxynitriding and stabilizing silicon carbide attached to an inner wall surface of a growth furnace; after the stabilization step, a bringing step of bringing a substrate in the growth furnace; and after the bringing step, a growth step of epitaxially growing a silicon carbide epitaxial layer on the substrate by supplying a process gas into the growth furnace to manufacture a silicon carbide epitaxial wafer.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Akihito OHNO, Kenichi HAMANO, Takashi KANAZAWA
  • Patent number: 10370775
    Abstract: A silicon carbide epitaxial wafer manufacturing method includes: a stabilization step of nitriding, oxidizing or oxynitriding and stabilizing silicon carbide attached to an inner wall surface of a growth furnace; after the stabilization step, a bringing step of bringing a substrate in the growth furnace; and after the bringing step, a growth step of epitaxially growing a silicon carbide epitaxial layer on the substrate by supplying a process gas into the growth furnace to manufacture a silicon carbide epitaxial wafer.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: August 6, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihito Ohno, Kenichi Hamano, Takashi Kanazawa
  • Patent number: 8303722
    Abstract: There is provided a storage water of a silicon wafer wherein a liquid temperature of the storage water is 0 to 18° C. And there is provided a shower water of a silicon wafer wherein a liquid temperature of the shower water is 0 to 18° C. The wafer is stored in the storage water, and showered using the shower water. The present invention also relates to a method for storing silicon wafer wherein the silicon wafer is showered using a shower water of which liquid temperature is 0 to 18° C., and is then stored in liquid using a storage water of which liquid temperature is 0 to 18° C. Thereby, there can be provided a water for storing a silicon wafer, a method for storing it, a water for showering it and a method for showering it wherein degradation of the wafer quality can be prevented.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: November 6, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tatsuo Abe, Kenichi Kanazawa, Akira Miyashita, Norio Kashimura
  • Patent number: 7486379
    Abstract: An exposure apparatus for exposing a substrate to light via an original plate. A projection optical system projects a pattern of the original plate onto the substrate, a liquid immersion mechanism generates a liquid immersion state in which a gap between the final surface of the projection optical system and the substrate is filled with liquid, a first photosensor detects light which has passed through the projection optical system, a second photosensor, different from the first photosensor, detects light that has passed through the projection optical system, and a controller calibrates an output from the first photosensor in the liquid immersion state based on a first output from the first photosensor in the liquid immersion state, a second output from the first photosensor in a non-liquid immersion state, and a third output from a reference illuminometer.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: February 3, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenichi Kanazawa
  • Publication number: 20060238734
    Abstract: An exposure apparatus for exposing a substrate to light via an original plate includes a projection optical system configured to project a pattern of the original plate onto the substrate, a liquid immersion mechanism configured to generate a liquid immersion state in which the gap between the projection optical system and the substrate is filled with liquid, a first photosensor configured to detect light which has passed through the projection optical system, and a controller configured to calibrate an output from the first photosensor in the liquid immersion state based on a first output from the first photosensor in the liquid immersion state, a second output from the first photosensor in a non liquid immersion state, and a third output from a reference illuminometer for detecting light which has passed through the projection optical system in the non liquid immersion state.
    Type: Application
    Filed: April 6, 2006
    Publication date: October 26, 2006
    Inventor: Kenichi Kanazawa
  • Publication number: 20030139067
    Abstract: There is provided a storage water of a silicon wafer wherein a liquid temperature of the storage water is 0 to 18° C. And there is provided a shower water of a silicon wafer wherein a liquid temperature of the shower water is 0 to 18° C. The wafer is stored in the storage water, and showered using the shower water. The present invention also relates to a method for storing silicon wafer wherein the silicon wafer is showered using a shower water of which liquid temperature is 0 to 18° C., and is then stored in liquid using a storage water of which liquid temperature is 0 to 18° C. Thereby, there can be provided a water for storing a silicon wafer, a method for storing it, a water for showering it and a method for showering it wherein degradation of the wafer quality can be prevented.
    Type: Application
    Filed: November 15, 2002
    Publication date: July 24, 2003
    Inventors: Tatsuo Abe, Kenichi Kanazawa, Akira Miyashita, Norio Kashimura
  • Patent number: 6326254
    Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: December 4, 2001
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Taiji Ema, Satoru Miyoshi, Tatsumi Tsutsui, Masaya Katayama, Masayoshi Asano, Kenichi Kanazawa
  • Patent number: 6251721
    Abstract: After an SAC film is formed to a thickness not to fill the spaces between gate electrodes in a memory cell region, a silicon oxide film is formed to a thickness to fill the spaces. A side wall made of a silicon oxide film is formed on the side surface of only a gate electrode in a peripheral circuit region, and a metal silicide is formed on the exposed substrate surface. A BLC film is formed on the entire surface. A contact hole is formed in self alignment using the SAC film and the BLC film. In this method, silicidation of the source/drain of a transistor in the peripheral circuit region and the self-alignment technique such as BLC or SAC can be simultaneously used to enable an increase in the degree of integration and improvement of performance of a semiconductor device having a metal silicide on the transistor in the logic circuit.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: June 26, 2001
    Assignee: Fujitsu Limited
    Inventors: Kenichi Kanazawa, Koichi Hashimoto, Yoshihiro Takao, Masaki Katsube
  • Patent number: 5789788
    Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: August 4, 1998
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Taiji Ema, Satoru Miyoshi, Tatsumi Tsutsui, Masaya Katayama, Masayoshi Asano, Kenichi Kanazawa
  • Patent number: 5767579
    Abstract: A terminal base (N1) is electrically connected to a conductive foil pattern (201), and a terminal base (N2) is electrically connected to switching elements (T1, T2, T3). The control electrodes of the switching elements (T1, T2, T3) are electrically connected to resistors (R10, R20, R30) with wire lines (WL). Thus, by using the resistors on which the wire lines can be bonded direct, a size-reduced semiconductor device is provided.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: June 16, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenichi Kanazawa, Kiyoshi Arai
  • Patent number: 4882768
    Abstract: An FM communication device employs a logarithmic amplifier which performs logarithmic conversion of a frequency modulated signal. The beat component level of the output signal of the logarithmic amplifier is checked with a reference level for detecting interference. With the construction set forth above, the FM communication device, according to the invention, detects the ripple of the received FM signal caused by interference of another FM signal by means of the logarithmic amplifier which converts the received FM signal logarithmically and the detection circuit which AM-detects the output signal of the logarithmic amplifier, so that the interference can be detected via the output signal of the detection circuit. In the preferred construction set forth above, the logarithmic amplifier which is often utilized in a detection system for reception magnitude is sufficient as an amplifier circuit required for detecting the interference, and no high-gain and high-performance amplifier is required.
    Type: Grant
    Filed: March 11, 1988
    Date of Patent: November 21, 1989
    Assignee: Sony Corporation
    Inventors: Bunichi Obana, Kenichi Kanazawa
  • Patent number: 4210827
    Abstract: A control circuit uses an adjustable resistance to generate a first control signal whose amplitude varies with the setting of the resistance and a second, step-like control signal whose level changes from a first to a second level at a predetermined setting of the resistance. The variable resistance is coupled to the collector of one of a pair of transistors whose emitters are commonly connected to a reference potential. The adjustable resistance's tap, which provides the first control signal, is connected to the base of the one transistor. A collector impedance and the variable resistance are coupled between the collector circuit of the one transistor and a voltage source. An output of the impedance is connected to the base of the other transistor, whose collector provides the second control signal.
    Type: Grant
    Filed: August 10, 1978
    Date of Patent: July 1, 1980
    Assignee: Sony Corporation
    Inventors: Kenichi Kanazawa, Yukio Tanaka
  • Patent number: 4161022
    Abstract: A controllable rectifier circuit which may be used in a power supply selectively produces a half-wave or a full-wave rectified signal. The rectifier circuit includes a pair of input terminals for receiving an AC signal and a bridge rectifier coupled to the input terminals and including a pair of output terminals across which a rectified AC signal is produced. The bridge rectifier comprises a first current path including a switchable rectifier for conducting positive half cycles of the AC signal and a second current path including a switchable rectifier for conducting negative half cycles of the AC signal. A pulse generator is supplied with reduced amplitude versions of the positive and negative half cycles of the AC signal, in sequence, to produce an output pulse when the reduced amplitude of the half cycle supplied thereto is less than a predetermined level.
    Type: Grant
    Filed: August 7, 1978
    Date of Patent: July 10, 1979
    Assignee: Sony Corporation
    Inventors: Kenichi Kanazawa, Nobuyuki Takahashi
  • Patent number: D399800
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: October 20, 1998
    Assignee: Bridgestone Corporation
    Inventors: Yasuo Himuro, Hiroshi Sato, Kenichi Kanazawa