Abstract: A flow controller for controlling a flow rate of a fluid flowing through a fluid passage comprises a control valve for which a degree of opening of a valve is adjusted by a control signal, an orifice arranged on an outflow side of the control valve, a combined sensor arranged on an inflow side of the orifice for almost simultaneously detecting a pressure and a temperature of the fluid, and a control circuit. The combined sensor includes a pressure-detecting element for deriving a detection signal corresponding to the pressure of the fluid, and a temperature-detecting element for deriving a detection signal corresponding to the temperature of the fluid. The pressure-detecting element and the temperature-detecting element are arranged closely to one another on an identical surface of a pressure-receiving section.

Abstract: The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.

Abstract: A computer and a backup computer exchange periodic report signal transmissions by way of SVP115. When there is no periodic report signal transmission from the main computer, the backup computer makes a main computer status inquiry and if one location is malfunctioning resets the main computer by way of the SVP115 and continues the processing. When permanent damage is present, the SVP115 continually resets the main computer and controls MOS switches of the common disk unit to isolate the SCSI from the main computer and continue the main computer processing.

Abstract: There is provided an input/output device which is capable of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal thereof. An expansion device 800 includes an electronic circuit 400 and a MOS switch 300 and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 is coupled to two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state; and, inside the expansion device, the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260.

Abstract: A suck back valve is equipped with a second valve by which a flow amount of a pressurized fluid, which is sucked by a third diaphragm, is electrically controlled based on an output of activation and deactivation signals from a main controller. The suck back valve further includes an encoder which detects a displacement amount of the third diaphragm, and outputs a detection signal thereof to the main controller.

Abstract: A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

Abstract: A suck back valve is equipped with a displacement speed regulating device made up of an ER (Electro-rheological) fluid filled in a chamber and whose viscosity changes in correspondence with the size of an external electric field, a coil member which generates the external electric field in response to an applied voltage, and a constriction which regulates a flow amount of the ER fluid between an upper-side chamber and a lower-side chamber of the chamber.

Abstract: A suck back valve is equipped with a first flow amount control device for controlling a pilot pressure supplied to an ON/OFF valve, and a second flow amount control device for controlling a pilot pressure supplied to a suck back mechanism, wherein the first and second flow amount control devices are operated based on activating and deactivating signals output from a main controller.

Abstract: The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.

Abstract: A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.

Abstract: A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

Abstract: A highly reliable computer system is intended to duplicate processors, compare the outputs of the processors with each other and enhance the validity of the output of processor system. If a mismatch between the outputs is detected, one of the processors performs a process of saving an internal state of the processor in amain memory and diagnosing factor of the detected mismatch. If the process is recognized to be continued in a duplex mode, the processors are re-synchronized by a processor reset, and initialize themselves and restore the internal information saved in the main memory for continuing the process having been proceeded before the fault occurred.

Abstract: A computer memory system is disclosed with an input/output circuitry capable of separating the load separating the load capacitance of an output circuit of a semiconductor memory connected to a memory bus from the memory bus. In order to separate the load capacitance of a semiconductor memory connected to a memory bus signal line, a Schottky diode is arranged between the semiconductor memory and the memory bus line, and a voltage control circuit is provided to control whether a reverse bias voltage is applied to the Schottky diode. The speed of signal transmission does not decrease even when a large number of semiconductor memories are connected to the memory bus since the load capacitance of the semiconductor memories is separated from the bus. Therefore, it is possible to construct a high speed and large capacity memory system.

Abstract: A parallel processing apparatus which includes a program counter for indicating instructions to be read out from a memory, an instruction register for storing a plurality of consecutive instructions read out from an address of the memory indicated by the program counter, a plurality of integer logic arithmetic units for executing integer-arithmetic operations, a floating-point arithmetic unit for executing floating-point-arithmetic operations, and a control unit for controlling the plurality of integer-logic arithmetic units and the floating-point arithmetic unit to effect either parallel processing of a plurality of consecutive instructions stored in the instruction register in the plurality of integer-logic arithmetic units and the floating-point arithmetic unit, or successive processing of instructions stored in the instruction register in response to a processing state alteration instruction. The apparatus also includes a branch arithmetic unit for executing branch arithmetic operations.

Abstract: A storage area for holding instantiation is provided together with a work area in order to rapidly generate a conflict set. When a condition of a rule is met, the instantiation of the rule is stored in the storage area in a form of data structure. The instantiation having an element whose attribute has been modified in an execution part of the rule is deleted from the conflict set.

Abstract: When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.

Abstract: A prefetch buffer adapted to be installed between a cache memory and a main memory in a computer system having a CPU. The prefetch buffer includes a buffer storage having at least one entry for storing prefetched data and an address tag, which is to be used for searching the data, as a pair; a data searcher for searching, from the data stored in the buffer storage, for data having an address requested by the CPU; and an address estimator for determining an address of data to be prefetched next from the main memory, based on the address requested by the CPU and also on a history of the addresses of data prefetched in the past from the main memory; and an address generator for generating an address of data to be prefetched from the main memory. With this arrangement, it is possible to improve the hit ratio of the prefetch buffer regardless of the direction in which the access address varies.

Abstract: High-speed inference method and system for a production system represented by an expert system. A knowledge base comprised of a rule and a fact possessing a plurality of attributes is converted into machine language instructions executable by a processor to execute inference. The machine language instruction of the fact has the function of transferring a value of the fact to a specified location and the machine language instruction of the rule has the function of performing matching decision by referring to the specified location. The number of pattern matching operations can be decreased and the interpretation overhead can be reduced to ensure high-speed inference.

Abstract: When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.

Abstract: A one-pack type thermosetting composition comprising (A) at least one polyisocyanate compound having dispersed therein (B) at least one compound selected from the group consisting of (1) a solid polyfunctional compound having at least one functional group selected from the group consisting of hydrazino, primary amido and sulfamoyl groups, (2) a solid compound having at least one amidino group and (3) a solid compound having a heterocyclic ring and a plurality of active hydrogen atoms, or a one-pack type thermosetting composition comprising (A') a mixture consisting of (a) at least one polyisocyanate compound and (b) at least one high boiling polar compound, having dispersed therein (B') a solid polyfunctional compound having at least one active hydrogen atom. Said one-pack type thermosetting composition is storable and suitable for use in adhesives, sealing materials, coatings and shaped articles of resin.