Patents by Inventor Kenichi Maruko
Kenichi Maruko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210159871Abstract: A semiconductor device according to an embodiment of the present disclosure includes an output driver including a first variable resistor element, a replica circuit including a second variable resistor element and having the same configuration as the output driver, a first wiring line coupled to an output end of the replica circuit; a second wiring line electrically coupled to a first external terminal; and a comparator that compares a voltage of the first wiring line with a voltage of the second wiring line.Type: ApplicationFiled: March 18, 2019Publication date: May 27, 2021Inventors: Shogo Hachiya, Kenichi Maruko, Koki Uchino, Makoto Imamura, Takamichi Iwaki, Nobuyuki Asai
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Patent number: 10951389Abstract: The operation range of a phase detector provided with a flip-flop is improved, and the jitter tolerance of a receiving circuit is enhanced. The phase detector includes a holding unit and a detection unit. In the phase detector, the holding unit holds an input signal in synchronization with a predetermined periodic signal. The detection unit detects a phase difference between a designated edge and the predetermined periodic signal on the basis of a signal held in the holding unit. The designated edge is designated by a control signal that designates one of a rising edge and a falling edge of the input signal as the designated edge.Type: GrantFiled: September 9, 2016Date of Patent: March 16, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Zhiwei Zhou, Takashi Masuda, Kenichi Maruko
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Patent number: 10845863Abstract: The electronic device includes a master element and a plurality of slave elements that are daisy-chain-connected. The slave element includes an input terminal connected to a slave element adjacently provided on the opposite side of the master element, an output terminal connected to the slave element adjacently provided on the side of the master element or the master element, and a first switch that is provided in a section between the input terminal and the output terminal used as a transmission path of transmission data and is connected to the transmission path in series. The master element receives the transmission data transmitted from the slave element to be the transmission source via the transmission path, and at least the slave element to be the transmission source includes a data transmission unit that is connected to the transmission path via a second switch and transmits the transmission data.Type: GrantFiled: March 15, 2017Date of Patent: November 24, 2020Assignee: SONY CORPORATIONInventors: Kenji Konda, Kenichi Maruko, Hideyuki Suzuki
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Publication number: 20200259630Abstract: The operation range of a phase detector provided with a flip-flop is improved, and the jitter tolerance of a receiving circuit is enhanced. The phase detector includes a holding unit and a detection unit. In the phase detector, the holding unit holds an input signal in synchronization with a predetermined periodic signal. The detection unit detects a phase difference between a designated edge and the predetermined periodic signal on the basis of a signal held in the holding unit. The designated edge is designated by a control signal that designates one of a rising edge and a falling edge of the input signal as the designated edge.Type: ApplicationFiled: September 9, 2016Publication date: August 13, 2020Inventors: ZHIWEI ZHOU, TAKASHI MASUDA, KENICHI MARUKO
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Publication number: 20190086989Abstract: The present technology relates to an electronic device, a driving method, and a slave element capable of obtaining sufficient transmission characteristics with low power consumption. The electronic device includes a master element and a plurality of slave elements that are daisy-chain-connected. The slave element includes an input terminal connected to a slave element adjacently provided on the opposite side of the master element, an output terminal connected to the slave element adjacently provided on the side of the master element or the master element, and a first switch that is provided in a section between the input terminal and the output terminal used as a transmission path of transmission data and is connected to the transmission path in series.Type: ApplicationFiled: March 15, 2017Publication date: March 21, 2019Inventors: KENJI KONDA, KENICHI MARUKO, HIDEYUKI SUZUKI
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Patent number: 10177878Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.Type: GrantFiled: January 12, 2017Date of Patent: January 8, 2019Assignee: SONY CORPORATIONInventors: Kazuhisa Funamoto, Tatsuo Shinbashi, Tatsuya Sugioka, Kenichi Maruko, Naohiro Koshisaka, Hiroo Takahashi
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Publication number: 20170126361Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.Type: ApplicationFiled: January 12, 2017Publication date: May 4, 2017Inventors: Kazuhisa Funamoto, Tatsuo Shinbashi, Tatsuya Sugioka, Kenichi Maruko, Naohiro Koshisaka, Hiroo Takahashi
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Patent number: 9565424Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.Type: GrantFiled: November 30, 2012Date of Patent: February 7, 2017Assignee: SONY CORPORATIONInventors: Kazuhisa Funamoto, Tatsuo Shinbashi, Tatsuya Sugioka, Kenichi Maruko, Naohiro Koshisaka, Hiroo Takahashi
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Patent number: 9407480Abstract: An apparatus according to an embodiment of the present disclosure includes a plurality of target circuits, the number of the target circuits being more than a required number of the target circuits; a characteristic adjustment unit configured to adjust characteristics of the target circuits; and a control unit configured to control a state of the target circuits between a used state and an unused state. The control unit controls the required number of the target circuits to be in the used state and controls the rest of the target circuits to be in the unused state. The characteristic adjustment unit adjusts the characteristics with respect to the target circuits in the unused state.Type: GrantFiled: February 19, 2015Date of Patent: August 2, 2016Assignee: Sony CorporationInventors: Takashi Yokokawa, Kenichi Maruko
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Patent number: 9350527Abstract: There is provided a reception unit, including: a transition detection section configured to detect a transition of an input data signal; an oscillation section configured to generate a clock signal and vary a phase of the clock signal based on a result of detection made by the transition detection section, the clock signal having a frequency in accordance with a first control signal; a first sampling section configured to sample the input data signal based on the clock signal and thereby generate an output data signal; and a control section configured to generate the first control signal based on the input data signal, the output data signal, and the clock signal.Type: GrantFiled: March 24, 2015Date of Patent: May 24, 2016Assignee: SONY CORPORATIONInventors: Takashi Masuda, Yosuke Ueno, Zhiwei Zhou, Kenichi Maruko, Jeremy Chatwin
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Publication number: 20150256154Abstract: An apparatus according to an embodiment of the present disclosure includes a plurality of target circuits, the number of the target circuits being more than a required number of the target circuits; a characteristic adjustment unit configured to adjust characteristics of the target circuits; and a control unit configured to control a state of the target circuits between a used state and an unused state. The control unit controls the required number of the target circuits to be in the used state and controls the rest of the target circuits to be in the unused state. The characteristic adjustment unit adjusts the characteristics with respect to the target circuits in the unused state.Type: ApplicationFiled: February 19, 2015Publication date: September 10, 2015Inventors: Takashi Yokokawa, Kenichi Maruko
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Patent number: 9065607Abstract: A clock data recovery circuit includes: an oscillator that outputs a clock signal; a phase comparator that outputs a signal corresponding to a phase difference between an input reception data signal and the clock signal; a divider that outputs a feedback clock signal; a first variable delay circuit that outputs a delay data signal; a second variable delay circuit that outputs a delay feedback clock signal; a frequency phase comparator that outputs a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal; a lock detector that outputs a determination signal indicating whether or not the frequency difference and the phase difference are within a predetermined range; and a multiplexer that receives the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator.Type: GrantFiled: November 20, 2013Date of Patent: June 23, 2015Assignee: Sony CorporationInventors: Kenichi Maruko, Yosuke Ueno
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Patent number: 9054689Abstract: A phase comparison circuit includes: a first flip-flop configured to receive a data signal and a clock signal; a second flip-flop configured to receive an output signal of the first flip-flop and a signal that is an inversion of logic of the clock signal; a delay circuit configured to give delay time to the data signal, in which the delay time is equal to or longer than signal delay time from a clock terminal of the first flip-flop to a Q output terminal of the first flip-flop; a first exclusive OR circuit configured to receive an output signal of the delay circuit and the output signal of the first flip-flop; and a second exclusive OR circuit configured to receive the output signal of the first flip-flop and an output signal of the second flip-flop.Type: GrantFiled: January 16, 2014Date of Patent: June 9, 2015Assignee: SONY CORPORATIONInventor: Kenichi Maruko
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Patent number: 8970312Abstract: There is provided a differential ring oscillation circuit including a differential ring oscillation unit in which delay circuits, to which signals of 2 phases are input, and which delay and output the input signals of 2 phases, are connected at even stages in a ring form, first and second common-mode level detection units that detect that the input signals of 2 phases of one delay circuit at an even stage of the differential ring oscillation unit and the input signals of 2 phases of one delay circuit at an odd stage of the differential ring oscillation unit are at same predetermined levels, respectively, and first and second switches that set, to specific potentials, one of the output signals of 2 phases of the delay circuit delaying the input signals of 2 phases, when the first and second common-mode level detection units detect the same predetermined levels, respectively.Type: GrantFiled: August 5, 2013Date of Patent: March 3, 2015Assignee: Sony CorporationInventors: Kenichi Maruko, Masayuki Katakura
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Patent number: 8970750Abstract: An image outputting apparatus includes a header production section for producing a header including header information formed from first and second frame information regarding whether pixel data included in a payload are of first and last lines of one frame, respectively, first line information regarding whether or not the pixel data included in the payload are valid, and second line information regarding a line number of a line formed from the pixel data included in the payload, and an error detection code for use for detection of an error of the header information. A packet production section produces a packet which includes, in the payload thereof, pixel data for one line which configure an image obtained by imaging by an imaging section and to which the header is added. An outputting section outputs the produced packet to an image processing apparatus.Type: GrantFiled: September 23, 2011Date of Patent: March 3, 2015Assignee: Sony CorporationInventors: Tatsuya Sugioka, Hiroshi Shiroshita, Miho Ozawa, Hiroki Kihara, Kenichi Maruko, Tatsuo Shinbashi, Kazuhisa Funamoto, Hideyuki Matsumoto, Takayuki Toyama, Hayato Wakabayashi, Naohiro Koshisaka, Shigetoshi Sasaki, Masato Tamori
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Patent number: 8964073Abstract: The present disclosure provides an image outputting apparatus, including, an image pickup section, an error correction code calculation section adapted to calculate an error correction code using pixel data, which configure an image obtained by image pickup by the image pickup section, as an information word, and an outputting section adapted to output coded data, which are data of a codeword obtained by adding the error correction code to the pixel data, to an image processing apparatus provided in an apparatus in which the image outputting apparatus is provided.Type: GrantFiled: October 20, 2011Date of Patent: February 24, 2015Assignee: Sony CorporationInventors: Kazuhisa Funamoto, Tatsuo Shinbashi, Hideyuki Matsumoto, Hiroshi Shiroshita, Hiroki Kihara, Kenichi Maruko, Tatsuya Sugioka, Naohiro Koshisaka, Shigetoshi Sasaki, Masato Tamori, Takayuki Toyama, Miho Ozawa, Hayato Wakabayashi
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Publication number: 20140300755Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.Type: ApplicationFiled: November 30, 2012Publication date: October 9, 2014Inventors: Kazuhisa Funamoto, Tatsuo Shinbashi, Tatsuya Sugioka, Kenichi Maruko, Naohiro Koshisaka, Hiroo Takahashi
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Patent number: 8812938Abstract: Disclosed herein is a coding apparatus, including: a calculation section adapted to calculate, based on information of a transmission object, a linear code to be used for error detection of the information; a production section adapted to produce coded data including a plurality of sets of the information and the linear code calculated by the calculation section; and a transmission section adapted to transmit the coded data to a reception apparatus.Type: GrantFiled: October 20, 2011Date of Patent: August 19, 2014Assignee: Sony CorporationInventors: Naohiro Koshisaka, Tatsuo Shinbashi, Kazuhisa Funamoto, Hideyuki Matsumoto, Hiroshi Shiroshita, Kenichi Maruko, Tatsuya Sugioka
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Publication number: 20140203842Abstract: A phase comparison circuit includes: a first flip-flop configured to receive a data signal and a clock signal; a second flip-flop configured to receive an output signal of the first flip-flop and a signal that is an inversion of logic of the clock signal; a delay circuit configured to give delay time to the data signal, in which the delay time is equal to or longer than signal delay time from a clock terminal of the first flip-flop to a Q output terminal of the first flip-flop; a first exclusive OR circuit configured to receive an output signal of the delay circuit and the output signal of the first flip-flop; and a second exclusive OR circuit configured to receive the output signal of the first flip-flop and an output signal of the second flip-flop.Type: ApplicationFiled: January 16, 2014Publication date: July 24, 2014Applicant: Sony CorporationInventor: Kenichi Maruko
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Publication number: 20140177771Abstract: A clock data recovery circuit includes: an oscillator that outputs a clock signal; a phase comparator that outputs a signal corresponding to a phase difference between an input reception data signal and the clock signal; a divider that outputs a feedback clock signal; a first variable delay circuit that outputs a delay data signal; a second variable delay circuit that outputs a delay feedback clock signal; a frequency phase comparator that outputs a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal; a lock detector that outputs a determination signal indicating whether or not the frequency difference and the phase difference are within a predetermined range; and a multiplexer that receives the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator.Type: ApplicationFiled: November 20, 2013Publication date: June 26, 2014Applicant: SONY CORPORATIONInventors: Kenichi Maruko, Yosuke Ueno