Patents by Inventor Kenichi Mimuro

Kenichi Mimuro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7851867
    Abstract: An integrated circuit includes: a semiconductor substrate that has a well region containing a first conductivity type impurity; and an enhancement type MOS transistor and a plurality of depletion type MOS transistors, each of which is formed in the well region and has a channel region under a gate electrode. At least one of the depletion type MOS transistors has, in the channel region, an implantation region into which a second conductivity type impurity is implanted so that a threshold voltage is adjusted. The implantation region has the first conductivity type impurity and the second conductivity type impurity. Further, the second conductivity type impurity has a concentration that is higher than a concentration of the first conductivity type impurity.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Chinatsu Seto, Mikiya Uchida, Kenichi Mimuro, Emi Kanazaki