Abstract: An object of the present invention is to provide a gardenia blue pigment that exhibits a vivid blue tone that is bright and has reduced redness, and a method for producing the gardenia blue pigment. A gardenia blue pigment that exhibits a vivid blue tone that is bright and has reduced redness is obtained by carrying out the following first and second steps: the first step of reacting at least one peptide selected from the group consisting of soy peptide, sesame peptide, and rice peptide with genipin in a solvent without the supply of a gas containing oxygen; and the second step of treating the reaction solution obtained in the first step with the supply of a gas containing oxygen.

Abstract: An object of the present invention is to provide a gardenia blue pigment that can stably maintain the color tone even after heating under acidic conditions, and a method for producing the gardenia blue pigment. A gardenia blue pigment that can stably maintain the color tone even after heating under acidic conditions is obtained by carrying out the following first and second steps: the first step of reacting walnut peptide, bitter melon peptide, and/or soy peptide with genipin in a solvent without the supply of a gas containing oxygen; and the second step of treating the reaction solution obtained in the first step with the supply of a gas containing oxygen.

Abstract: A battery state estimation device includes a detecting part, a state of charge (SOC) estimating part, an open circuit voltage (OCV) estimating part, a terminal voltage estimating part, and a correcting part. The detecting part detects a charge-discharge current and a terminal voltage of a battery. The SOC estimating part estimates an SOC of the battery, based on the charge-discharge current detected by the detecting part. The OCV estimating part estimates an OCV of the battery, based on the SOC estimated by the SOC estimating part and a relationship between an OCV and the SOC of the battery. The terminal voltage estimating part calculates an estimated terminal voltage, based on the charge-discharge current and the terminal voltage detected by the detecting part and on an equivalent circuit model constructed using an inversely proportional curve.

Abstract: A battery state estimation device includes a detecting part, a state of charge (SOC) estimating part, an open circuit voltage (OCV) estimating part, a terminal voltage estimating part, and a correcting part. The detecting part detects a charge-discharge current and a terminal voltage of a battery. The SOC estimating part estimates an SOC of the battery, based on the charge-discharge current detected by the detecting part. The OCV estimating part estimates an OCV of the battery, based on the SOC estimated by the SOC estimating part and a relationship between an OCV and the SOC of the battery. The terminal voltage estimating part calculates an estimated terminal voltage, based on the charge-discharge current and the terminal voltage detected by the detecting part and on an equivalent circuit model constructed using an inversely proportional curve.

Abstract: A memory allocation/free replacing unit hooks a call of a memory allocating/freeing unit. The memory allocation/free replacing unit generates information required for totalization of a dynamically used memory amount, writes the generated information to a log file, and calls the memory allocating/freeing unit to perform memory allocation and free. A totalization processing unit loads the log file and totalizes a dynamically used memory amount for each dynamic library, for each function, or for each thread.

Abstract: An information processing system in which a plurality of information processing apparatuses are connected with each other, wherein each information processing apparatus includes a storage unit configured to store data according to each destination information processing apparatus, and a transmission control unit configured to transmit data to be transmitted in the same transmission direction and with the same number of hops collectively among the data stored in the storage unit.

Abstract: A foam filler is provided with a base for forming a foam and placed inside a hollow structure having a through hole. An opening having an area larger than the opening of the through hole is created in the base and surrounding the through hole. The foam filler is provided with an upper wall which follows the flow and the thermal expansion of the base at the time of heating. The upper wall closes at least part of the opening of the through hole when following the flow and the thermal expansion of the base, and thus prevents the base from entering into the through hole. The upper wall is provided in a peripheral portion of the opening and placed in a part of an area surrounding the through hole.

Abstract: A foam filler is provided with a base for forming a foam and placed inside a hollow structure having a through hole. An opening having an area larger than the opening of the through hole is created in the base and surrounding the through hole. The foam filler is provided with an upper wall which follows the flow and the thermal expansion of the base at the time of heating. The upper wall closes at least part of the opening of the through hole when following the flow and the thermal expansion of the base, and thus prevents the base from entering into the through hole. The upper wall is provided in a peripheral portion of the opening and placed in a part of an area surrounding the through hole.

Abstract: A void filling device which facilitates insertion of a void filling material into a tubular component and hold of the void filling material therewithin. The device comprises a holder for void filling material which is designed to retain the void filling material to fill a void space by expanding with heat and is of a different material from the void filling material so as to be elastically deformed and inserted into the void space. When the cross-sectional configuration of the void space of the tubular component is a rectangle, the holder is formed into a plate-like configuration which is longer than the diagonal line of the rectangle and is adapted to be insertable into the void space by bending the same arcuately.

Abstract: A void filling device which facilitates insertion of a void filling material into a tubular component and hold of the void filling material therewithin. The device comprises a holder for void filling material which is designed to retain the void filling material to fill a void space by expanding with heat and is of a different material from the void filling material so as to be elastically deformed and inserted into the void space When the cross-sectional configuration of the void space of the tubular component is a rectangle, the holder is formed into a plate-like configuration which is longer than the diagonal line of the rectangle and is adapted to be insertable into the void space by bending the same arcuately.

Abstract: In a sterescopic camera supporting apparatus of this invention, first and second image pickup elements incorporated in first and second cameras which are independent of each other so as to obtain a stereoscopic image are attached to corresponding holders by elongated apertures formed in mounting portions of the first and second cameras and screws loosely fitted in the elongated apertures, so as to be pivotally adjusted in plane directions perpendicular to optical axes of the first and second cameras. The first camera is attached to a first sub frame by elongated apertures formed in the mounting portion of the first camera and screws loosely fitted in the elongated apertures to be vertically pivoted about the optical axis for adjustment.

Abstract: Decoder and method utilizing logic circuitry for decoding multi-bit digital signals. An input decoder decodes subsets of the input signals to provide a plurality of intermediate signals which are selectively combined to provide output signals which represent a desired decoding of the input signals. The intermediate signals are applied to generally parallel bus lines which extend centrally of the substrate on which the decoder is constructed. The logic circuits are arranged in blocks along both sides of the bus lines, with all of the bus lines extending past all of the logic blocks, and conductors extending transversely of the bus lines carry the appropriate intermediate signals from the bus lines to the logic blocks.

Abstract: A parity prediction circuit for predicting parity in an adder, counter or similar device. The parity prediction is obtained with a parity prediction network connected from most significant bit to least significant bit. The parity prediction network is used in place of a parity generator or in combination with a parity generator for error checking purposes. In a special application, the parity prediction is employed for a ripple-carry type counter where the predicted parity bit is produced by a single network of NAND gates connected in series from high-order to low-order counter bits. The predicted parity is available no later than the completion of the carry-out propagation.

Abstract: An arithmetic and logic unit (ALU) formed by a small number of different types of basic cells suitable for cellular integration to form large scale integrated (LSI) semiconductor circuits. The arithmetic and logic unit is formed from a plurality of 1-bit ALU cells. Each ALU cell is formed by a plurality of cellular integrated basic cells where each ALU cell includes two data inputs, A and B, and responsively produces a data output, F. Each ALU cell has provision for some type of carry circuit, carry ripple or carry look-ahead. In a carry ripple example, the 1-bit ALU cells are of two basic types, an odd type and an even type. The carry-out from an odd type cell is connected as a carry-in to an even type cell and similarly, the carry-out of an even type cell is connected as a carry-in to an odd type cell. The arithmetic and logic unit is formed by a plurality of alternating odd and even 1-bit ALU cells.

Abstract: A tree-type combinatorial logic circuit comprising a plurality of identical functional units which may be arranged to operate as an N-bit magnitude comparator, a carry generator for an N-bit adder, or a parity predictor for 2N-bit binary counter. Each of the units is provided with four input terminals and two output terminals. The units are arranged to form a binary tree. Each unit has an internal logic circuit which generates outputs of G.sub.K*l =G.sub.K VE.sub.K .multidot.g.sub.l and E.sub.K*l =E.sub.K .multidot.E.sub.l, where "V" and ".multidot." denote Boolean OR and AND operations, respectively. The desired functions are provided at the output terminals of the unit in the final stage of the tree.The input signals to the units in the first stage of the tree depend on the applications of the circuit. When used as a magnitude comparator, the inputs are a.sub.i .multidot.b.sub.i 's and a.sub.i.sup..sym. b.sub.i 's (i=0, 1,..., N-1), where a.sub.i and b.sub.