Patents by Inventor Kenichi Miura
Kenichi Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136034Abstract: There are provided an information processing apparatus, an information processing method, an endoscope system, and a report creation support device which can efficiently input information on a treatment name. The information processing apparatus includes a first processor. The first processor acquires an image captured using an endoscope, displays the acquired image in a first region on a screen of a first display unit, detects a treatment tool from the acquired image, chooses a plurality of treatment names corresponding to the detected treatment tool, displays the plurality of chosen treatment names in a second region on the screen of the first display unit, and accepts selection of one treatment name from among the plurality of displayed treatment names.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: FUJIFILM CorporationInventors: Yuma HORI, Yuya KIMURA, Tatsuya KOBAYASHI, Kenichi HARADA, Goro MIURA, Shungo ASANO, Hiromu SHIMPO
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Publication number: 20240100474Abstract: A mixed gas separation method includes a step of supplying a mixed gas to the separation membrane and causing a gas with high permeability in the mixed gas to permeate through the separation membrane. In the step, when ?P is a difference between a gas pressure on the primary side of the separation membrane, i.e., a feed pressure, and a gas pressure on the secondary side of the separation membrane, i.e., a permeate pressure, and A is a Joule-Thomson coefficient, a difference ?T between a gas temperature on the primary side of the separation membrane, i.e., a feed temperature, and a gas temperature on the secondary side of the separation membrane, i.e., a permeate temperature, is made less than 90% of A·?P by setting the Nu number in the mixed gas to be greater than or equal to 2 and less than or equal to 10.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Applicant: NGK INSULATORS, LTD.Inventors: Ko KOBAYASHI, Katsuya SHIMIZU, Aya MIURA, Kenichi NODA
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Publication number: 20240092953Abstract: The present invention provides a novel copolymer available for a drug delivery technique. More particularly, a novel copolymer for a drug delivery carrier targeting a tumor is provided. The present invention relates to a copolymer comprising structural units represented by the following formulas (A), (B), and (C): wherein R1, R2, and R3 are the same or different and represent a hydrogen atom or a C1-3 alkyl group, R4 represents a C1-3 alkyl group, R5 represents a hydrogen atom, a C1-18 alkyl group, a 3- to 8-membered cycloalkyl group optionally having a substituent, an adamantyl group, a C6-18 aryl group optionally having a substituent, or a 5- to 10-membered heteroaryl group optionally having a substituent, X1, X2, and X3 are the same or different and represent an oxygen atom, a sulfur atom, or N—R7, R6 represents a hydrogen atom, a leaving group, or a linker, R7 represents a hydrogen atom or a C1-3 alkyl group, m represents an integer of 1 to 100, and n represents an integer of 0 to 3.Type: ApplicationFiled: February 7, 2022Publication date: March 21, 2024Applicant: KOWA COMPANY, LTD.Inventors: Ryo KANAYA, Kenichi SUZUKI, Tsukasa CHIDA, Nobuhiro FUJIMAKI, Marina ECHIGO, Seiji MIURA
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Publication number: 20240078483Abstract: An information processing apparatus includes a controller that acquires information about an article to be loaded onto a vehicle, acquires a characteristic of a person who can affect the article based on the information, and executes a concurrent riding determination to determine existence of concurrent riding on the vehicle by the article and a user having the characteristic.Type: ApplicationFiled: September 5, 2023Publication date: March 7, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Mitsuhiro MIURA, Kenichi YAMADA, Satoshi KOMAMINE, Fumiyuki KAGARA, Go TANAKA, Hiroyuki NISHIZAWA
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Publication number: 20240070576Abstract: An information processing apparatus includes a memory that stores information on a package to be transported by a vehicle traveling within a site of a factory and attributes of each employee working at the factory, a controller that sets a condition on an employee who can be in charge of loading or unloading the package and formulates a transportation plan for the package based on the information on the package, and identifies at least one employee who has attributes satisfying the condition, from among one or more employees scheduled to ride in the vehicle transporting the package, based on the attributes of each employee and the condition on the employee who can be in charge of loading or unloading the package, and a communication interface that notifies a mobile terminal carried by the at least one employee of a request for loading or unloading the package.Type: ApplicationFiled: August 24, 2023Publication date: February 29, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Mitsuhiro MIURA, Kenichi YAMADA, Satoshi KOMAMINE, Fumiyuki KAGARA, Go TANAKA, Hiroyuki NISHIZAWA
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Patent number: 10345386Abstract: A battery state estimation device includes a detecting part, a state of charge (SOC) estimating part, an open circuit voltage (OCV) estimating part, a terminal voltage estimating part, and a correcting part. The detecting part detects a charge-discharge current and a terminal voltage of a battery. The SOC estimating part estimates an SOC of the battery, based on the charge-discharge current detected by the detecting part. The OCV estimating part estimates an OCV of the battery, based on the SOC estimated by the SOC estimating part and a relationship between an OCV and the SOC of the battery. The terminal voltage estimating part calculates an estimated terminal voltage, based on the charge-discharge current and the terminal voltage detected by the detecting part and on an equivalent circuit model constructed using an inversely proportional curve.Type: GrantFiled: February 27, 2015Date of Patent: July 9, 2019Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Toru Omi, Kenichi Miura, Satoru Hiwa, Takuma Iida, Kazushige Kakutani
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Publication number: 20170176540Abstract: A battery state estimation device includes a detecting part, a state of charge (SOC) estimating part, an open circuit voltage (OCV) estimating part, a terminal voltage estimating part, and a correcting part. The detecting part detects a charge-discharge current and a terminal voltage of a battery. The SOC estimating part estimates an SOC of the battery, based on the charge-discharge current detected by the detecting part. The OCV estimating part estimates an OCV of the battery, based on the SOC estimated by the SOC estimating part and a relationship between an OCV and the SOC of the battery. The terminal voltage estimating part calculates an estimated terminal voltage, based on the charge-discharge current and the terminal voltage detected by the detecting part and on an equivalent circuit model constructed using an inversely proportional curve.Type: ApplicationFiled: February 27, 2015Publication date: June 22, 2017Inventors: TORU OMI, KENICHI MIURA, SATORU HIWA, TAKUMA IIDA, KAZUSHIGE KAKUTANI
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Publication number: 20140215483Abstract: A memory allocation/free replacing unit hooks a call of a memory allocating/freeing unit. The memory allocation/free replacing unit generates information required for totalization of a dynamically used memory amount, writes the generated information to a log file, and calls the memory allocating/freeing unit to perform memory allocation and free. A totalization processing unit loads the log file and totalizes a dynamically used memory amount for each dynamic library, for each function, or for each thread.Type: ApplicationFiled: December 20, 2013Publication date: July 31, 2014Applicant: FUJITSU LIMITEDInventors: Hideyuki Akimoto, Yuichiro Ajima, Kenichi Miura, Takayuki Okamoto, Tomoya Adachi, Shinji Sumimoto
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Publication number: 20140201475Abstract: An information processing system in which a plurality of information processing apparatuses are connected with each other, wherein each information processing apparatus includes a storage unit configured to store data according to each destination information processing apparatus, and a transmission control unit configured to transmit data to be transmitted in the same transmission direction and with the same number of hops collectively among the data stored in the storage unit.Type: ApplicationFiled: November 22, 2013Publication date: July 17, 2014Applicant: FUJITSU LIMITEDInventors: Takafumi NOSE, Kenichi MIURA
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Patent number: 8726590Abstract: A foam filler is provided with a base for forming a foam and placed inside a hollow structure having a through hole. An opening having an area larger than the opening of the through hole is created in the base and surrounding the through hole. The foam filler is provided with an upper wall which follows the flow and the thermal expansion of the base at the time of heating. The upper wall closes at least part of the opening of the through hole when following the flow and the thermal expansion of the base, and thus prevents the base from entering into the through hole. The upper wall is provided in a peripheral portion of the opening and placed in a part of an area surrounding the through hole.Type: GrantFiled: September 21, 2007Date of Patent: May 20, 2014Assignee: Iida Industry Co., Ltd.Inventors: Kenichi Miura, Koichiro Ohbai, Koji Tokuyama
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Publication number: 20080073923Abstract: A foam filler is provided with a base for forming a foam and placed inside a hollow structure having a through hole. An opening having an area larger than the opening of the through hole is created in the base and surrounding the through hole. The foam filler is provided with an upper wall which follows the flow and the thermal expansion of the base at the time of heating. The upper wall closes at least part of the opening of the through hole when following the flow and the thermal expansion of the base, and thus prevents the base from entering into the through hole. The upper wall is provided in a peripheral portion of the opening and placed in a part of an area surrounding the through hole.Type: ApplicationFiled: September 21, 2007Publication date: March 27, 2008Inventors: Kenichi Miura, Koichiro Ohbai, Koji Tokuyama
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Patent number: 6887060Abstract: A void filling device which facilitates insertion of a void filling material into a tubular component and hold of the void filling material therewithin. The device comprises a holder for void filling material which is designed to retain the void filling material to fill a void space by expanding with heat and is of a different material from the void filling material so as to be elastically deformed and inserted into the void space. When the cross-sectional configuration of the void space of the tubular component is a rectangle, the holder is formed into a plate-like configuration which is longer than the diagonal line of the rectangle and is adapted to be insertable into the void space by bending the same arcuately.Type: GrantFiled: June 25, 2002Date of Patent: May 3, 2005Assignee: Iida Industry Co., Ltd.Inventors: Kenichi Miura, Akira Yamada
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Publication number: 20030003174Abstract: A void filling device which facilitates insertion of a void filling material into a tubular component and hold of the void filling material therewithin. The device comprises a holder for void filling material which is designed to retain the void filling material to fill a void space by expanding with heat and is of a different material from the void filling material so as to be elastically deformed and inserted into the void space When the cross-sectional configuration of the void space of the tubular component is a rectangle, the holder is formed into a plate-like configuration which is longer than the diagonal line of the rectangle and is adapted to be insertable into the void space by bending the same arcuately.Type: ApplicationFiled: June 25, 2002Publication date: January 2, 2003Inventors: Kenichi Miura, Akira Yamada
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Patent number: 4879596Abstract: In a sterescopic camera supporting apparatus of this invention, first and second image pickup elements incorporated in first and second cameras which are independent of each other so as to obtain a stereoscopic image are attached to corresponding holders by elongated apertures formed in mounting portions of the first and second cameras and screws loosely fitted in the elongated apertures, so as to be pivotally adjusted in plane directions perpendicular to optical axes of the first and second cameras. The first camera is attached to a first sub frame by elongated apertures formed in the mounting portion of the first camera and screws loosely fitted in the elongated apertures to be vertically pivoted about the optical axis for adjustment.Type: GrantFiled: January 5, 1989Date of Patent: November 7, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Miura, Hiromichi Kobayashi
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Patent number: 4438427Abstract: Decoder and method utilizing logic circuitry for decoding multi-bit digital signals. An input decoder decodes subsets of the input signals to provide a plurality of intermediate signals which are selectively combined to provide output signals which represent a desired decoding of the input signals. The intermediate signals are applied to generally parallel bus lines which extend centrally of the substrate on which the decoder is constructed. The logic circuits are arranged in blocks along both sides of the bus lines, with all of the bus lines extending past all of the logic blocks, and conductors extending transversely of the bus lines carry the appropriate intermediate signals from the bus lines to the logic blocks.Type: GrantFiled: July 20, 1978Date of Patent: March 20, 1984Assignee: Fujitsu LimitedInventor: Kenichi Miura
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Patent number: 4224680Abstract: A parity prediction circuit for predicting parity in an adder, counter or similar device. The parity prediction is obtained with a parity prediction network connected from most significant bit to least significant bit. The parity prediction network is used in place of a parity generator or in combination with a parity generator for error checking purposes. In a special application, the parity prediction is employed for a ripple-carry type counter where the predicted parity bit is produced by a single network of NAND gates connected in series from high-order to low-order counter bits. The predicted parity is available no later than the completion of the carry-out propagation.Type: GrantFiled: June 5, 1978Date of Patent: September 23, 1980Assignee: Fujitsu LimitedInventor: Kenichi Miura
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Patent number: 4218747Abstract: An arithmetic and logic unit (ALU) formed by a small number of different types of basic cells suitable for cellular integration to form large scale integrated (LSI) semiconductor circuits. The arithmetic and logic unit is formed from a plurality of 1-bit ALU cells. Each ALU cell is formed by a plurality of cellular integrated basic cells where each ALU cell includes two data inputs, A and B, and responsively produces a data output, F. Each ALU cell has provision for some type of carry circuit, carry ripple or carry look-ahead. In a carry ripple example, the 1-bit ALU cells are of two basic types, an odd type and an even type. The carry-out from an odd type cell is connected as a carry-in to an even type cell and similarly, the carry-out of an even type cell is connected as a carry-in to an odd type cell. The arithmetic and logic unit is formed by a plurality of alternating odd and even 1-bit ALU cells.Type: GrantFiled: June 5, 1978Date of Patent: August 19, 1980Assignee: Fujitsu LimitedInventor: Kenichi Miura
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Patent number: 4163211Abstract: A tree-type combinatorial logic circuit comprising a plurality of identical functional units which may be arranged to operate as an N-bit magnitude comparator, a carry generator for an N-bit adder, or a parity predictor for 2N-bit binary counter. Each of the units is provided with four input terminals and two output terminals. The units are arranged to form a binary tree. Each unit has an internal logic circuit which generates outputs of G.sub.K*l =G.sub.K VE.sub.K .multidot.g.sub.l and E.sub.K*l =E.sub.K .multidot.E.sub.l, where "V" and ".multidot." denote Boolean OR and AND operations, respectively. The desired functions are provided at the output terminals of the unit in the final stage of the tree.The input signals to the units in the first stage of the tree depend on the applications of the circuit. When used as a magnitude comparator, the inputs are a.sub.i .multidot.b.sub.i 's and a.sub.i.sup..sym. b.sub.i 's (i=0, 1,..., N-1), where a.sub.i and b.sub.Type: GrantFiled: April 17, 1978Date of Patent: July 31, 1979Assignee: Fujitsu LimitedInventor: Kenichi Miura