Abstract: A transmitting apparatus includes: a first processor circuit; a second processor circuit; a modulation circuit; and a switch circuit, wherein the first processor circuit is configured to execute a generating process that includes mapping each of a plurality of bit strings to a symbol in predetermined order for each number of bits according to a multivalued degree of a multilevel modulation method, and generating a symbol information piece according to the symbol, wherein the modulation circuit is configured to modulate light in accordance with the symbol information piece based on the multilevel modulation method; wherein the second processor circuit is configured to execute a detecting process that includes detecting each of inputs of a plurality of data signals, wherein the switch circuit is configured to select the plurality of bit strings based on a detection result of inputs of the plurality of data signals.

Abstract: A transmitting apparatus includes: a first processor circuit; a second processor circuit; a modulation circuit; and a switch circuit, wherein the first processor circuit is configured to execute a generating process that includes mapping each of a plurality of bit strings to a symbol in predetermined order for each number of bits according to a multivalued degree of a multilevel modulation method, and generating a symbol information piece according to the symbol, wherein the modulation circuit is configured to modulate light in accordance with the symbol information piece based on the multilevel modulation method; wherein the second processor circuit is configured to execute a detecting process that includes detecting each of inputs of a plurality of data signals, wherein the switch circuit is configured to select the plurality of bit strings based on a detection result of inputs of the plurality of data signals,

Abstract: A transmission apparatus includes a logic circuit for performing a predetermined process, and outputting a logic output signal depending on the process, an open-drain signal generation circuit, connectable at an input terminal to the logic circuit and at an output terminal to a pull-up resistor, and a transmission path failure determination circuit for determining whether there is a failure in a transmission path which transmits a signal outputted from the logic circuit via the open-drain signal generation circuit, wherein the transmission path failure determination circuit includes an edge waveform information obtaining circuit for obtaining edge waveform information indicating a waveform of at least one of a rising edge and a falling edge of an application signal, and a failure determination circuit for determining whether the edge waveform information satisfies a predetermined condition, and outputting a failure signal indicating that there is a failure in the transmission path.

Abstract: A transmission apparatus includes a logic circuit for performing a predetermined process, and outputting a logic output signal depending on the process, an open-drain signal generation circuit, connectable at an input terminal to the logic circuit and at an output terminal to a pull-up resistor, and a transmission path failure determination circuit for determining whether there is a failure in a transmission path which transmits a signal outputted from the logic circuit via the open-drain signal generation circuit, wherein the transmission path failure determination circuit includes an edge waveform information obtaining circuit for obtaining edge waveform information indicating a waveform of at least one of a rising edge and a falling edge of an application signal, and a failure determination circuit for determining whether the edge waveform information satisfies a predetermined condition, and outputting a failure signal indicating that there is a failure in the transmission path.

Abstract: A control apparatus that controls one or more first communication apparatuses and one or more second communication apparatuses configured to identify a logic level of a signal, the control apparatus includes a memory; and a processor coupled to the memory and configured to: acquire, from one of the one or more second communication apparatuses, a length of an undefined time period during which a level of the signal is undefined; determine, based on the length of the undefined time period, a length of a protection time period indicating a time period during which a logic level of the signal received by the second communication apparatus is maintained at a same level; and determine, based on the length of the protection time period, a rate of a signal transmitted to one of the one or more second communication apparatuses by one of the one or more first communication apparatuses.

Abstract: A control apparatus that controls one or more first communication apparatuses and one or more second communication apparatuses configured to identify a logic level of a signal, the control apparatus includes a memory; and a processor coupled to the memory and configured to: acquire, from one of the one or more second communication apparatuses, a length of an undefined time period during which a level of the signal is undefined; determine, based on the length of the undefined time period, a length of a protection time period indicating a time period during which a logic level of the signal received by the second communication apparatus is maintained at a same level; and determine, based on the length of the protection time period, a rate of a signal transmitted to one of the one or more second communication apparatuses by one of the one or more first communication apparatuses.

Abstract: An FPGA configuration device comprises: a read operation control unit which performs control to read configuration data from a configured FPGA; and a configuration data transfer unit which transfers the configuration data read out of the FPGA to a memory.

Abstract: A configuration data feeding device for feeding configuration data to a plurality of FPGAs includes a memory for storing configuration data that are fed to the plurality of FPGAs, a plurality of interface units for outputting the configuration data read out from the memory, according to their specific configuration layouts, an interface selection unit for selecting, out of the plurality of interface units, an interface unit that is to be used for configuring each of the plurality of FPGAs, and a circuit-switching unit for switching the circuits that connect the FPGAs to the interface units depending upon the selection by the interface selection unit.

Abstract: A configuration data feeding device for feeding configuration data to a plurality of FPGAs includes a memory for storing configuration data that are fed to the plurality of FPGAs, a plurality of interface units for outputting the configuration data read out from the memory, according to their specific configuration layouts, an interface selection unit for selecting, out of the plurality of interface units, an interface unit that is to be used for configuring each of the plurality of FPGAs, and a circuit-switching unit for switching the circuits that connect the FPGAs to the interface units depending upon the selection by the interface selection unit.

Abstract: A transmission apparatus that does not include a plurality of switches, that cross-connects a signal, and that can handle various redundancy settings determined by a user. An address information generation section generates address information indicative of the destination of a signal, from redundancy setting information and cross connect setting information. An activation information setting section activates and deactivates activation information included in the address information when failure occurs. An address information insertion section inserts the address information stored in an address information storage section into the signal and outputs the signal to a bus. A signal output section receives the signal having the address information that is the same as own address information and outputs the signal to a next stage in the case of the activation information indicating activation.

Abstract: An FPGA configuration device comprises: a read operation control unit which performs control to read configuration data from a configured FPGA; and a configuration data transfer unit which transfers the configuration data read out of the FPGA to a memory.

Abstract: A transmission apparatus that does not include a plurality of switches, that cross-connects a signal, and that can handle various redundancy settings determined by a user. An address information generation section generates address information indicative of the destination of a signal, from redundancy setting information and cross connect setting information. An activation information setting section activates and deactivates activation information included in the address information when failure occurs. An address information insertion section inserts the address information stored in an address information storage section into the signal and outputs the signal to a bus. A signal output section receives the signal having the address information that is the same as own address information and outputs the signal to a next stage in the case of the activation information indicating activation.