Patents by Inventor Kenichi Morioka

Kenichi Morioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240095126
    Abstract: A PWM control circuit is configured to control the operation of an external circuit, and stop operations upon input of an anomaly detection signal from an externally provided anomaly detection circuit. A voltage detection circuit is configured to detect a change in the voltage value of a power source voltage and generate and output a hardware reset signal. A reset circuit outputs a reset signal to reset an entire device if the hardware reset signal from the voltage detection circuit, a software reset signal from a CPU, or the anomaly detection signal becomes active.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 21, 2024
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Kenichi MORIOKA
  • Publication number: 20230315482
    Abstract: A microcontroller unit (MCU) includes a central processing unit (CPU) that reads a program from a flash read-only memory (ROM) and executes a process, a remapping register that stores a read destination of the flash ROM to be read by the CPU, an overwrite flag register that stores a flag that determines whether or not to overwrite the program stored in the flash ROM when the CPU is reset, and a dedicated remapping reset register that resets the CPU and the remapping register but does not reset the overwrite flag register when a value indicating resetting of the CPU and the remapping register is written thereto.
    Type: Application
    Filed: March 20, 2023
    Publication date: October 5, 2023
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Kenichi MORIOKA
  • Publication number: 20220247447
    Abstract: A notification response circuit includes a reception coil, a characteristic variable circuit connected to the reception coil, and a switch control circuit. The reception coil is configured to generate a current based on an external electromagnetic field. The characteristic variable circuit includes at least two circuits of a variable capacitor circuit, a voltage output circuit, and a variable resistor circuit. The variable capacitor circuit is configured to change a capacitance. The voltage output circuit is configured to change a voltage value between a pair of connection lines disposed between the reception coil and the voltage output circuit according to a voltage value of a reference voltage. The variable resistor circuit is configured to change a resistance value. The switch control circuit selectively switches any of the at least two circuits and performs control to change impedances of the reception coil and a circuit part connected to the reception coil.
    Type: Application
    Filed: May 27, 2020
    Publication date: August 4, 2022
    Inventor: KENICHI MORIOKA
  • Patent number: 8885895
    Abstract: A fingerprint authentication device includes: a fingerprint acquisition section that acquires fingerprint image data; a fingerprint image correction processing section that corrects a pixel value by using a correction coefficient for making a first pixel value of the brightest pixel in a group of pixels at which an integrated value of a number of pixels at a dark portion side in a histogram becomes a predetermined proportion with respect to an integrated value of a number of all pixels, be a brighter second pixel value; a spectral data generation section that generates a spectral data matrix including directions of ridges of a fingerprint and a frequency of the fingerprint; a registered spectral data matrix archive section that archives a registered spectral data matrix; a fingerprint verification section that verifies the spectral data matrix and the registered spectral data matrix; and an authentication results output section that outputs results of authentication.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: November 11, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventors: Kenichi Morioka, Hirofumi Muramatsu
  • Publication number: 20120106808
    Abstract: A fingerprint authentication device includes: a fingerprint acquisition section that acquires fingerprint image data; a fingerprint image correction processing section that corrects a pixel value by using a correction coefficient for making a first pixel value of the brightest pixel in a group of pixels at which an integrated value of a number of pixels at a dark portion side in a histogram becomes a predetermined proportion with respect to an integrated value of a number of all pixels, be a brighter second pixel value; a spectral data generation section that generates a spectral data matrix including directions of ridges of a fingerprint and a frequency of the fingerprint; a registered spectral data matrix archive section that archives a registered spectral data matrix; a fingerprint verification section that verifies the spectral data matrix and the registered spectral data matrix; and an authentication results output section that outputs results of authentication.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 3, 2012
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Kenichi Morioka, Hirofumi Muramatsu
  • Publication number: 20100040306
    Abstract: There is provided an image processing method for acquiring a partial image a target and constructing one whole image of the target. The acquired partial image is stored in a first storage section. A movement amount of an image is calculated using a previous partial image and a latest partial image. A partial image having a minimum difference from the latest partial image in an overlapping portion therebetween is stored in a second storage section. The partial image having the minimum difference as the latest partial image in the first storage section is stored when it is determined that the calculated movement amount is more than the predetermined value.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 18, 2010
    Inventors: Kenichi Morioka, Shingo Kazuma
  • Publication number: 20070288724
    Abstract: Halting clocks of pipeline registers 28-31 and data memory 26, etc., and holding input data of each of FE, DC, MEM, WB stages, during when a nop is sent to each of pipelines, by a first process for outputting a nop signal S41 of logic level “H” when the nop is detected by a nop detecting circuit 41, a second process for sending the detected nop signal to each of the pipelines by F/Fs 46-48 placed between each of the pipelines, and a third process for halting clocks by clock control circuits 42-45 placed in each of the pipelines when the nop signal is sent to each of the pipelines.
    Type: Application
    Filed: March 29, 2007
    Publication date: December 13, 2007
    Inventors: Hiroki Goko, Kenichi Morioka