Abstract: Provided is a jitter injection apparatus that injects jitter into a signal, comprising: a plurality of jitter injecting sections that are provided in series in a transmission path that propagates the signal; an output section that selects the signal that is passed from a jitter injecting section at a first stage through a designated jitter injecting section, and outputs the selected signal; and a plurality of branch-path jitter injecting sections that (i) are provided in a plurality of branch paths that propagate the signal output by each jitter injecting section from the transmission path to the output section and (ii) are relays having frequency characteristics of attenuating a high-frequency band more than a low-frequency band.

Abstract: A test apparatus for testing a device under test includes a capture memory that stores thereon an output pattern received from the device under test, a header detecting section that reads the output pattern from the capture memory and detects a portion matching a predetermined header pattern in the output pattern, and a judging section that judges whether the output pattern is acceptable based on a result of comparison between a pattern, in the output pattern, which starts with the portion matching the predetermined header pattern and a corresponding expected value pattern.

Abstract: Provided is a transfer characteristic measurement apparatus that measures a transfer characteristic of a circuit under test between input and output, comprising a test signal input section that generates a test signal by adding together a carrier signal having a prescribed frequency and an additional signal having a frequency that differs from the prescribed frequency, and inputs the test signal to the circuit under test; and a transfer characteristic measuring section that measures the transfer characteristic of the circuit under test at the frequency of the additional signal based on a result from a measurement of an output signal output by the circuit under test. The circuit under test may be formed on a semiconductor chip. The circuit under test may correct a signal input to the semiconductor chip, and outputs the corrected signal. The semiconductor chip may further include a sampling circuit that samples the output signal of the circuit under test at the frequency of the carrier signal.

Abstract: A test apparatus includes a transmitting-side jitter measuring unit which measures a jitter of a transmission signal output from a transmitting circuit, a jitter applying unit which applies a jitter to the transmission signal and inputs the signal to a receiving circuit, a jitter range measuring unit which determines whether the logical value of the transmission signal detected by the receiving circuit is equal to a preset expectation value for each amplitude of the jitter applied to the transmission signal by the jitter applying unit, and measures the range of jitter amplitudes within which the logical value of the transmission signal is equal to the expectation value, and a jitter tolerance measuring unit which calculates jitter tolerance of the receiving circuit based on the jitter of the transmission signal measured by the transmitting-side jitter measuring unit and the range of jitter amplitudes measured by the jitter range measuring unit.

Abstract: Provided is a test apparatus that tests a device under test, wherein the device under test includes an internal circuit that generates a plurality of internal clocks having different phases based on a reference clock provided thereto, selects from among the internal clocks an internal clock having a predetermined relative phase with respect to an input signal having a frequency substantially equal to that of the internal clocks, and samples the input signal according to the selected internal clock.

Abstract: Provided is a transfer characteristic measurement apparatus that measures a transfer characteristic of a circuit under test between input and output, comprising a test signal input section that generates a test signal by adding together a carrier signal having a prescribed frequency and an additional signal having a frequency that differs from the prescribed frequency, and inputs the test signal to the circuit under test; and a transfer characteristic measuring section that measures the transfer characteristic of the circuit under test at the frequency of the additional signal based on a result from a measurement of an output signal output by the circuit under test. The circuit under test may be formed on a semiconductor chip. The circuit under test may correct a signal input to the semiconductor chip, and outputs the corrected signal. The semiconductor chip may further include a sampling circuit that samples the output signal of the circuit under test at the frequency of the carrier signal.

Abstract: Provided is a jitter injection circuit that injects jitter having a predetermined amplitude to a transmission signal outputted from a transmission circuit, and inputs the resulting transmission signal to a reception circuit, the jitter injection circuit including: a retiming section that receives the transmission signal from the transmission circuit, and performs retiming on an edge timing of the received transmission signal in accordance with a given clock signal; and a jitter injection section that injects the jitter having the predetermined amplitude to the transmission signal outputted from the retiming section, and inputs the resulting transmission signal to the reception circuit.

Abstract: Provided is a jitter injection apparatus that injects jitter into a signal, comprising: a plurality of jitter injecting sections that are provided in series in a transmission path that propagates the signal; an output section that selects the signal that is passed from a jitter injecting section at a first stage through a designated jitter injecting section, and outputs the selected signal; and a plurality of branch-path jitter injecting sections that (i) are provided in a plurality of branch paths that propagate the signal output by each jitter injecting section from the transmission path to the output section and (ii) are relays having frequency characteristics of attenuating a high-frequency band more than a low-frequency band

Abstract: Provided is a jitter injection circuit that injects jitter having a predetermined amplitude to a transmission signal outputted from a transmission circuit, and inputs the resulting transmission signal to a reception circuit, the jitter injection circuit including: a retiming section that receives the transmission signal from the transmission circuit, and performs retiming on an edge timing of the received transmission signal in accordance with a given clock signal; and a jitter injection section that injects the jitter having the predetermined amplitude to the transmission signal outputted from the retiming section, and inputs the resulting transmission signal to the reception circuit.

Abstract: A test apparatus includes a transmitting-side jitter measuring unit which measures a jitter of a transmission signal output from a transmitting circuit, a jitter applying unit which applies a jitter to the transmission signal and inputs the signal to a receiving circuit, a jitter range measuring unit which determines whether the logical value of the transmission signal detected by the receiving circuit is equal to a preset expectation value for each amplitude of the jitter applied to the transmission signal by the jitter applying unit, and measures the range of jitter amplitudes within which the logical value of the transmission signal is equal to the expectation value, and a jitter tolerance measuring unit which calculates jitter tolerance of the receiving circuit based on the jitter of the transmission signal measured by the transmitting-side jitter measuring unit and the range of jitter amplitudes measured by the jitter range measuring unit.

Abstract: It is aimed to efficiently test devices that can transfer data at a very high bit rate. A test apparatus for testing a device under test includes a capture memory that stores thereon an output pattern received from the device under test, a header detecting section that reads the output pattern from the capture memory and detects a portion matching a predetermined header pattern in the output pattern, and a judging section that judges whether the output pattern is acceptable based on a result of comparison between a pattern, in the output pattern, which starts with the portion matching the predetermined header pattern and a corresponding expected value pattern.

Abstract: A document reading apparatus comprises a light transmitting plate in contact with a document, a light source to light the document, a plurality of lenses arranged in line at a specified interval to image light reflected from the document and form a scaled-down document image, a plurality of semiconductor chips having a multiplicity of photoelectric transducer elements arranged in line respectively corresponding to each lens in order to receive the document image, a circuit wiring base plate on which semiconductor chips are placed, and a body unit to hold the light transmitting plate, the light source, and the circuit wiring base plate. The document image is formed in a scaled-down state by the plurality of lenses, and received by the plurality of semiconductor chips respectively corresponding to each lens. Since the document image is formed in a scaled-down state, it is not necessary to arrange the photoelectric transducer elements continuously between adjacent semiconductor chips.