Patents by Inventor Kenichi Narikawa
Kenichi Narikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11454664Abstract: A testing system includes: an inspection module including a plurality of levels of inspection chambers in each of which a tester part having a tester configured to perform an electrical inspection of an inspection object and a probe card is accommodated; an aligner module configured to align the inspection object with the tester part; an alignment area in which the aligner module is accommodated; and a loader part configured to load the inspection object into the alignment area and unload the inspection object out of the aligner module, wherein the inspection module is located adjacent to the alignment area.Type: GrantFiled: April 16, 2018Date of Patent: September 27, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Kentaro Konishi, Jun Fujihara, Hiroki Shikagawa, Hiroshi Yamada, Yukinori Murata, Katsuaki Sugiyama, Shin Uchida, Tetsuya Kagami, Hiroaki Hayashi, Rika Ozawa, Takanori Hyakudomi, Xingjun Jiang, Kenichi Narikawa, Tomoya Endo
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Patent number: 11293978Abstract: A voltage application device of a tester includes a voltage setting controller that sets a number of transient steps, step time, and step voltage as transient voltage setting parameters; and a device power supply (DPS) configured to supply power to the plurality of devices under test formed on a substrate. The voltage application device outputs an output voltage having a step-like transient voltage waveform based on the transient voltage setting parameters set by the voltage setting controller. The voltage application device is a high-order lag system of a second-order or higher in which an overshoot occurs in a response with respect to a set voltage. An end point of a step time of each of the transient steps set in the voltage setting controller is set to be a time between an end point of a rising time and an overshoot time.Type: GrantFiled: July 25, 2018Date of Patent: April 5, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Shigeki Ishii, Katsuaki Sugiyama, Kenichi Narikawa, Koji Shinagawa, Takumi Nagura
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Publication number: 20210333319Abstract: A testing system includes: an inspection module including a plurality of levels of inspection chambers in each of which a tester part having a tester configured to perform an electrical inspection of an inspection object and a probe card is accommodated; an aligner module configured to align the inspection object with the tester part; an alignment area in which the aligner module is accommodated; and a loader part configured to load the inspection object into the alignment area and unload the inspection object out of the aligner module, wherein the inspection module is located adjacent to the alignment area.Type: ApplicationFiled: April 16, 2018Publication date: October 28, 2021Inventors: Kentaro KONISHI, Jun FUJIHARA, Hiroki SHIKAGAWA, Hiroshi YAMADA, Yukinori MURATA, Katsuaki SUGIYAMA, Shin UCHIDA, Tetsuya KAGAMI, Hiroaki HAYASHI, Rika OZAWA, Takanori HYAKUDOMI, Xingjun JIANG, Kenichi NARIKAWA, Tomoya ENDO
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Patent number: 10859601Abstract: There is provided a device inspection circuit capable of measuring currents flowing through a plurality of devices without increasing the cost. A power supply circuit of a box-side inspection circuit includes an operational amplifier and a sense resistor. A power source having a current measuring function, the operational amplifier, the sense resistor and a DUT are connected in series in this order. The power source is connected to a non-inverting input terminal of the operational amplifier. The power supply circuit further includes a negative feedback channel configured to apply a voltage between the sense resistor and the DUT to an inverting input terminal of the operational amplifier, and a positive feedback channel configured to connect an upstream sense point between the operational amplifier and the sense resistor and the non-inverting input terminal of the operational amplifier. The positive feedback channel includes a feedback resistor installed therein.Type: GrantFiled: June 6, 2017Date of Patent: December 8, 2020Assignee: TOKYO ELECTRON LIMITEDInventor: Kenichi Narikawa
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Publication number: 20200278392Abstract: A voltage application device of a tester includes a voltage setting controller that sets a number of transient steps, step time, and step voltage as transient voltage setting parameters; and a device power supply (DPS) configured to supply power to the plurality of devices under test formed on a substrate. The voltage application device outputs an output voltage having a step-like transient voltage waveform based on the transient voltage setting parameters set by the voltage setting controller. The voltage application device is a high-order lag system of a second-order or higher in which an overshoot occurs in a response with respect to a set voltage. An end point of a step time of each of the transient steps set in the voltage setting controller is set to be a time between an end point of a rising time and an overshoot time.Type: ApplicationFiled: July 25, 2018Publication date: September 3, 2020Inventors: Shigeki Ishii, Katsuaki Sugiyama, Kenichi Narikawa, Koji Shinagawa, Takumi Nagura
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Publication number: 20190178913Abstract: There is provided a device inspection circuit capable of measuring currents flowing through a plurality of devices without increasing the cost. A power supply circuit of a box-side inspection circuit incudes an operational amplifier and a sense resistor. A power source having a current measuring function, the operational amplifier, the sense resistor and a DUT are connected in series in this order. The power source is connected to a non-inverting input terminal of the operational amplifier. The power supply circuit further includes a negative feedback channel configured to apply a voltage between the sense resistor and the DUT to an inverting input terminal of the operational amplifier, and a positive feedback channel configured to connect an upstream sense point between the operational amplifier and the sense resistor and the non-inverting input terminal of the operational amplifier. The positive feedback channel includes a feedback resistor installed therein.Type: ApplicationFiled: June 6, 2017Publication date: June 13, 2019Inventor: Kenichi NARIKAWA
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Publication number: 20190128952Abstract: A substrate inspection apparatus capable of suppressing deterioration of user convenience when inspecting a semiconductor device without separating the semiconductor device from a substrate is provided. A WLSLT apparatus 10, which is connected to a user controller 29 configured to control a PKGSLT apparatus 28 and configured to inspect a semiconductor device formed on a wafer W without separating the semiconductor device from the wafer W, includes a test program engine 27 configured to convert a command complying with a command protocol specific to the PKGSLT apparatus 28 into a command complying with a command protocol specific to the WLSLT apparatus 10.Type: ApplicationFiled: December 26, 2018Publication date: May 2, 2019Inventors: Katsuaki Sugiyama, Atsuo Mitsui, Yutaka Kosuga, Kenichi Narikawa
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Patent number: 10114070Abstract: A substrate inspection apparatus can efficiently inspect electric characteristics of the semiconductor device. A prober 10 includes a probe card 15 having a multiple number of probe needles 17 to be brought into contact with electrodes of a semiconductor device formed on a wafer W; and a test box 14 electrically connected to the probe card 15. A card-side inspection circuit of the probe card 15 reproduces a circuit configuration on which the semiconductor device is to be mounted after separated from the wafer W, e.g., the circuit configuration of a function extension card, and a box-side inspection circuit 21 of the test box 14 reproduces a circuit configuration on which the semiconductor device is to be mounted, e.g., a part of the circuit configuration of the mother board.Type: GrantFiled: September 16, 2014Date of Patent: October 30, 2018Assignee: TOKYO ELECTRON LIMITEDInventors: Michio Murata, Shingo Morita, Kenichi Narikawa
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Publication number: 20150077152Abstract: A substrate inspection apparatus can efficiently inspect electric characteristics of the semiconductor device. A prober 10 includes a probe card 15 having a multiple number of probe needles 17 to be brought into contact with electrodes of a semiconductor device formed on a wafer W; and a test box 14 electrically connected to the probe card 15. A card-side inspection circuit of the probe card 15 reproduces a circuit configuration on which the semiconductor device is to be mounted after separated from the wafer W, e.g., the circuit configuration of a function extension card, and a box-side inspection circuit 21 of the test box 14 reproduces a circuit configuration on which the semiconductor device is to be mounted, e.g., a part of the circuit configuration of the mother board.Type: ApplicationFiled: September 16, 2014Publication date: March 19, 2015Inventors: Michio Murata, Shingo Morita, Kenichi Narikawa
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Publication number: 20100289332Abstract: A negative polarity side of a positive-side parallel circuit and a positive polarity side of a negative-side parallel circuit are connected to a common potential point. Both parallel circuits have a primary-side power supply and a by-pass capacitor connected in parallel, respectively. A series circuit has one end connected to a positive polarity side of the positive-side parallel circuit and other end connected to a negative polarity side of the negative-side parallel circuit. A third switch has one end connected to a connection point between a first switch and a second switch of the series circuit and other end connected to the common potential point. A load has one end connected to a connection point of the first switch, the second switch and the third switch via an inductor and other end connected to the common potential point. A switch control circuit is configured to drive selectively respective switches.Type: ApplicationFiled: May 7, 2010Publication date: November 18, 2010Applicant: YOKOGAWA ELECTRIC CORPORATIONInventor: Kenichi NARIKAWA
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Patent number: 7733113Abstract: A semiconductor test device of the present invention for conducting a test on a device under test, includes: a plurality of comparison units which compare a signal obtained from the device under test with a predetermined reference voltage and output a comparison result; a plurality of measuring units which are provided in correspondence with the plurality of comparison units, and measure a time from when a measurement start signal is input thereto to when the comparison result from a corresponding comparison unit is input thereto, and output a measuring result; a start signal output unit which outputs the measurement start signal at a same timing to each of the plurality of measuring units; and a computation unit which computes time differences between a plurality of signals obtained from the device under test based on the measuring results of the plurality of measuring units.Type: GrantFiled: October 30, 2008Date of Patent: June 8, 2010Assignee: Yokogawa Electric CorporationInventor: Kenichi Narikawa
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Publication number: 20090121738Abstract: A semiconductor test device of the present invention for conducting a test on a device under test, includes: a plurality of comparison units which compare a signal obtained from the device under test with a predetermined reference voltage and output a comparison result; a plurality of measuring units which are provided in correspondence with the plurality of comparison units, and measure a time from when a measurement start signal is input thereto to when the comparison result from a corresponding comparison unit is input thereto, and output a measuring result; a start signal output unit which outputs the measurement start signal at a same timing to each of the plurality of measuring units; and a computation unit which computes time differences between a plurality of signals obtained from the device under test based on the measuring results of the plurality of measuring units.Type: ApplicationFiled: October 30, 2008Publication date: May 14, 2009Applicant: Yokogawa Electric CorporationInventor: Kenichi NARIKAWA
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Patent number: 3950467Abstract: A method for shaping a tubular film in a downward and wet manner is provided in which an extruded tubular film is coagulated in contact with a coagulation liquid which flows down along the inside surface of a cylindrical composite perforated wall composed of a cylindrical perforated wall and cylindrically piled up circular rings of coiled wire provided in a single layer and in contact with the inner surface of said cylindrical perforated wall, provided in a negative pressure chamber connected to the lower part of a coagulation liquid-supplying pool; in this coagulation, coagulation liquid is fully utilized by mixing with a reflux coagulation liquid formed when a part of coagulation liquid once flows out through said wall and is collected in a plurality of coagulation liquid-collecting weirs provided around the outer surface of said wall, and then flows again through said wall to the inside thereof; and said film is drawn downward while being supported on the inner surface of said wall by friction due to suctiType: GrantFiled: February 6, 1974Date of Patent: April 13, 1976Assignee: Polymer Processing Research Institute Ltd.Inventors: Masahide Yazawa, Kazuhiko Kurihara, Kenichi Narikawa, Hirosi Yazawa