Abstract: A clock signal generation circuit includes a first oscillation circuit for generating a first oscillation clock signal having a first frequency; a second oscillation circuit for generating a second oscillation clock signal having a second frequency; a frequency division circuit for generating a frequency division clock signal obtained through dividing the first oscillation clock signal; and a clock selection circuit for outputting the first oscillation clock signal as a high speed clock signal. The clock selection circuit is configured to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal, and to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.

Abstract: A clock signal generation circuit includes a first oscillation circuit for generating a first oscillation clock signal having a first frequency; a second oscillation circuit for generating a second oscillation clock signal having a second frequency; a frequency division circuit for generating a frequency division clock signal obtained through dividing the first oscillation clock signal; and a clock selection circuit for outputting the first oscillation clock signal as a high speed clock signal. The clock selection circuit is configured to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal, and to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.

Abstract: A data transmission circuit includes a first clock generating circuit that generates a first clock; a second clock generating circuit that generates a second clock, which is different from the first clock; a serial interface circuit that supplies an output signal in synchronization with the first clock; and a latch circuit that latches the output signal, supplied from the serial interface circuit, in synchronization with the second clock, to generate a transmission data to be transmitted.

Abstract: There is provided an arithmetic circuit for minimizing the delay of data path from the input of data to be operated to the output of the result of operation of data. To that end, the arithmetic circuit comprises a first selector to which one input data and a fixed data are inputted wherein these data are selectively outputted in response to a control signal, a second selector to which another input data and an output data of a register are inputted wherein these data are selectively outputted in response to the control signal, an adder for receiving an output signal of the first selector and an output signal of the second selector to execute the addition of the output signals of the first and second selectors, and a register for receiving an output signal of the adder to hold the output signal in synchronization with a clock signal.

Abstract: The transposition circuit includes N input terminals (where N is an integer of 2 or greater) and N output terminals. This transposition circuit is configured such that when N packets of data for each matrix row are inputted in parallel to the corresponding input terminals, N packets of data are output in parallel for each matrix column from the corresponding output terminals. This transposition circuit generates data packets arranged as a transposed matrix and obtained from data packets in the form of an N×N matrix by interchanging the rows and columns of the original matrix.

Abstract: A scan test circuit includes a scan flip-flop that receives a reset signal, a data signal, a scan data signal, and a scan shift enable signal selecting either the data signal or the scan data signal. A reset control circuit controls the reset signal according to the scan shift enable signal. Even if the reset signal originates in a combinatorial circuit, the reset control circuit can prevent the flip-flop from being reset during a scan shift sequence, without the need for external control of the reset signal. Further control of the reset signal can be provided by a mask circuit. These reset control features enable improved fault coverage to be obtained with a reduced number of external input terminals, a reduced number of test patterns, and only a small amount of additional test circuitry.

Abstract: A data transmission circuit includes a first clock generating circuit that generates a first clock; a second clock generating circuit that generates a second clock, which is different from the first clock; a serial interface circuit that supplies an output signal in synchronization with the first clock; and a latch circuit that latches the output signal, supplied from the serial interface circuit, in synchronization with the second clock, to generate a transmission data to be transmitted.

Abstract: A picture decoding device of the present invention comprises a CPU, receiving as input encoded moving picture information, for subtracting ‘1’ from a slice start code inside slice information extracted from this information, a variable length code decoding circuit provided with a horizontal position generating circuit for subtracting ‘1’ from a macro block address (MBA) when output information formed from macro block position information (VP, HP), motion vectors, picture information etc. is output, using information output from the CPU, and a motion compensation circuit for carrying out decoding processing for the moving picture information, with origin coordinates set to (0,0), using a slice start code and macro block address after subtraction.

Abstract: Clock switching circuitry includes a clock switching control circuit for temporarily storing a clock select signal, which is input from the outside for selecting one of a plurality of clock signals different in phase from each other. The clock switching control circuit then outputs the clock select signal in accordance with the change in the level of a timing signal that switches the clock signals. A clock output circuit outputs one of the clock signals selected in accordance with the clock select signal. A masking circuit generates the timing signal while masking it to a preselected level by taking account of changes in the levels of the clock signals.

Abstract: There is provided an arithmetic circuit for minimizing the delay of data path from the input of data to be operated to the output of the result of operation of data. To that end, the arithmetic circuit comprises a first selector to which one input data and a fixed data are inputted wherein these data are selectively outputted in response to a control signal, a second selector to which another input data and an output data of a register are inputted wherein these data are selectively outputted in response to the control signal, an adder for receiving an output signal of the first selector and an output signal of the second selector to execute the addition of the output signals of the first and second selectors, and a register for receiving an output signal of the adder to hold the output signal in synchronization with a clock signal.

Abstract: The transposition circuit comprises N input terminals (where N is an integer of 2 or greater) and N output terminals. This transposition circuit is configured such that when N packets of data for each matrix row are inputted in parallel to the corresponding input terminals, N packets of data are outputted in parallel for each matrix column from the corresponding output terminals. This transposition circuit generates data packets arranged as a transposed matrix and obtained from data packets in the form of an N×N matrix by interchanging the rows and columns of the original matrix.

Abstract: A scan test circuit includes a scan flip-flop that receives a reset signal, a data signal, a scan data signal, and a scan shift enable signal selecting either the data signal or the scan data signal. A reset control circuit controls the reset signal according to the scan shift enable signal. Even if the reset signal originates in a combinatorial circuit, the reset control circuit can prevent the flip-flop from being reset during a scan shift sequence, without the need for external control of the reset signal. Further control of the reset signal can be provided by a mask circuit. These reset control features enable improved fault coverage to be obtained with a reduced number of external input terminals, a reduced number of test patterns, and only a small amount of additional test circuitry.

Abstract: A level-turning point of input data is detected; and a sampling clock is generated in response to the level-turning point of the input data. The input data are sampled in synchronization with the sampling clock.

Abstract: Clock switching circuitry includes a clock switching control circuit for temporarily storing a clock select signal, which is input from the outside for selecting one of a plurality of clock signals different in phase from each other. The clock switching control circuit then outputs the clock select signal in accordance with the change in the level of a timing signal that switches the clock signals. A clock output circuit outputs one of the clock signals selected in accordance with the clock select signal. A masking circuit generates the timing signal while masking it to a preselected level by taking account of changes in the levels of the clock signals.

Abstract: A picture decoding device of the present invention comprises a CPU, receiving as input encoded moving picture information, for subtracting ‘1’ from a slice start code inside slice information extracted from this information, a variable length code decoding circuit provided with a horizontal position generating circuit for subtracting ‘1’ from a macro block address (MBA) when output information formed from macro block position information (VP, HP), motion vectors, picture information etc. is output, using information output from the CPU, and a motion compensation circuit for carrying out decoding processing for the moving picture information, with origin coordinates set to (0,0), using a slice start code and macro block address after subtraction.

Abstract: A level-turning point of input data is detected; and a sampling clock is generated in response to the level-turning point of the input data. The input data are sampled in synchronization with the sampling clock.

Abstract: A level-turning point of input data is detected; and a sampling clock is generated in response to the level-turning point of the input data. The input data are sampled in synchronization with the sampling clock.

Abstract: A level-turning point of input data is detected; and a sampling clock is generated in response to the level-turning point of the input data. The input data are sampled in synchronization with the sampling clock.

Abstract: A data generating circuit includes a memory which writes picture data into a plurality of storage areas and reads the picture data from the plurality of storage areas according to address information. A register which hold information indicative whether the picture data has been written into each of the plurality of storage areas. A control circuit which outputs a select signal according to the storage information held by the register when the picture data is read from the memory. A selector which selects an output data read from the memory or a fixed data according to the select signal output by the control circuit.

Abstract: A level-turning point of input data is detected; and a sampling clock is generated in response to the level-turning point of the input data. The input data are sampled in synchronization with the sampling clock.