Abstract: AD conversion is performed by using a combination of a parallel AD converter that includes a plurality of comparators to compare an input potential of an analog input signal sampled by a track and hold circuit and reference potentials different from one another and determines a value of a predetermined number of bits on the higher-order side of a digital signal and a single-slope AD converter that reduces the input potential of the analog input signal sampled by the track and hold circuit at a constant speed, converts a time taken until the reduced input potential becomes equal to a reference potential corresponding to the value determined by the parallel AD converter to a digital value, and determines a remaining value on the lower-order side of the digital signal, and thereby the number of bits of the single-slope AD converter can be reduced and high-speed AD conversion is enabled with a small area and low power consumption.

Abstract: AD conversion is performed by using a combination of a parallel AD converter that includes a plurality of comparators to compare an input potential of an analog input signal sampled by a track and hold circuit and reference potentials different from one another and determines a value of a predetermined number of bits on the higher-order side of a digital signal and a single-slope AD converter that reduces the input potential of the analog input signal sampled by the track and hold circuit at a constant speed, converts a time taken until the reduced input potential becomes equal to a reference potential corresponding to the value determined by the parallel AD converter to a digital value, and determines a remaining value on the lower-order side of the digital signal, and thereby the number of bits of the single-slope AD converter can be reduced and high-speed AD conversion is enabled with a small area and low power consumption.

Abstract: A parallel-type AD converter includes: a plurality of comparators that receive comparison reference potentials different from one another and compare the comparison reference potentials and received analog input signals; an encoder that encodes outputs of the plurality of comparators to output digital signals; and a resistor ladder circuit that resistance-divides a reference voltage to generate the comparison reference potentials and supplies the comparison reference potentials to the comparators through output nodes each positioned between resistors, and is designed to supply a correction current corresponding to noise currents that the comparators generate to the output nodes of the comparison reference potentials in the resistor ladder circuit, and thereby the noise currents that the comparators generate are offset by the correction current, a bias current in the resistor ladder circuit can be decreased, and accuracy deterioration in AD conversion can be suppressed.

Abstract: A parallel-type AD converter includes: a plurality of comparators that receive comparison reference potentials different from one another and compare the comparison reference potentials and received analog input signals; an encoder that encodes outputs of the plurality of comparators to output digital signals; and a resistor ladder circuit that resistance-divides a reference voltage to generate the comparison reference potentials and supplies the comparison reference potentials to the comparators through output nodes each positioned between resistors, and is designed to supply a correction current corresponding to noise currents that the comparators generate to the output nodes of the comparison reference potentials in the resistor ladder circuit, and thereby the noise currents that the comparators generate are offset by the correction current, a bias current in the resistor ladder circuit can be decreased, and accuracy deterioration in AD conversion can be suppressed.

Abstract: The invention provides a transceiver circuit for communication that enhances the operation frequency of a synchronous digital circuit up to the maximum frequency of a flip-flop and inhibits the occurrence of jitters. A clock signal synchronized with data at f1/n Hz is converted by a multiplier so that the signal has a frequency of “n” times so as to use the clock signal for triggering a flip-flop the operation frequency of which is f1 b/s in the synchronous digital circuit. The multiplier is arranged in the vicinity of the flip-flop triggered by the clock signal of f1 Hz so as to avoid the effect of the deterioration of the operation frequency by interconnect capacitance. The maximum operation frequency of the transceiver circuit determined based upon the operating frequency of the synchronous digital circuit can be enhanced up to the maximum operation frequency of the flip-flop.

Abstract: A frequency generator which can perform stable frequency oscillation unaffected by temperature variation. A frequency generator having a differential amplifier (1) having an LC resonance circuit (10) as a load and buffer circuits (21, 22) feeding back an output of the differential amplifier to its input, wherein a temperature coefficient converter (5) converting an output voltage of a reference voltage generator (4) and its temperature dependence to a voltage having a predetermined voltage and temperature coefficient and outputting it is provided to control bias currents IEF of emitter follower circuits to be in proportion to temperature variation. There are a characteristic in which delay time of the emitter follower circuits constructing the buffer circuits is in inverse proportion to a transconductance of transistors and a characteristic in which the transconductance is in inverse proportion to temperature and is in proportion to the bias currents IEF.

Abstract: A frequency generator which can perform stable frequency oscillation unaffected by temperature variation. A frequency generator having a differential amplifier (1) having an LC resonance circuit (10) as a load and buffer circuits (21, 22) feeding back an output of the differential amplifier to its input, wherein a temperature coefficient converter (5) converting an output voltage of a reference voltage generator (4) and its temperature dependence to a voltage having a predetermined voltage and temperature coefficient and outputting it is provided to control bias currents IEF of emitter follower circuits to be in proportion to temperature variation. There are a characteristic in which delay time of the emitter follower circuits constructing the buffer circuits is in inverse proportion to a transconductance of transistors and a characteristic in which the transconductance is in inverse proportion to temperature and is in proportion to the bias currents IEF.

Abstract: The present invention provides an optical transmitter using a multiplexer which can maintain a timing margin between a clock and data as an operating reference at an optimal value when data transmission speed, or data rate to be handled is changed.

Abstract: A large time constant is caused due to parasitic capacitance at an anode terminal of a photodetector of an optical receiver. Therefore, an optical receiver wherein a variable negative capacitor mainly including an NPN-type transistor operable at high speed is configured and is connected to the input terminal of a preamplifier to which the output of the photodetector is input so that parasitic capacitance caused in the photodetector and due to packaging is equivalently reduced and the fluctuation of parasitic capacitance caused due to manufacturing dispersion is also compensated is provided.

Abstract: The invention provides a transceiver circuit for communication that enhances the operation frequency of a synchronous digital circuit up to the maximum frequency of a flip-flop and inhibits the occurrence of jitters.

Abstract: An optical receiver generates a voltage signal having a predetermined swing from a current signal, and feeds the voltage signal to a decision circuit. An optical receiving element receives the input optical signal, converts the optical signal to a current signal, and provides the current signal to a preamplifier, which converts the input current signal into a voltage signal. The voltage signal is input to an amplifier having a limiting function, which linearly amplifies the voltage signal when the swing of the voltage signal is smaller than a predetermined value, and limitedly amplifies the voltage signal when the voltage signal is greater than the predetermined value. An automatic-gain-control amplifier receives the output from the amplifier with the limiting function, and amplifies the input voltage signal to a voltage signal having a constant swing.

Abstract: An optical receiver generates a voltage signal having a predetermined swing from a current signal, and feeds the voltage signal to a decision circuit. An optical receiving element receives the input optical signal, converts the optical signal to a current signal, and provides the current signal to a preamplifier, which converts the input current signal into a voltage signal. The voltage signal is input to an amplifier having a limiting function, which linearly amplifies the voltage signal when the swing of the voltage signal is smaller than a predetermined value, and limitedly amplifies the voltage signal when the voltage signal is greater than the predetermined value. An automatic-gain-control amplifier receives the output from the amplifier with the limiting function, and amplifies the input voltage signal to a voltage signal having a constant swing.

Abstract: An optical receiver generates a voltage signal having a predetermined swing from a current signal, and feeds the voltage signal to a decision circuit. An optical receiving element receives the input optical signal, converts the optical signal to a current signal, and provides the current signal to a preamplifier, which converts the input current signal into a voltage signal. The voltage signal is input to an amplifier having a limiting function, which linearly amplifies the voltage signal when the swing of the voltage signal is smaller than a predetermined value, and limitedly amplifies the voltage signal when the voltage signal is greater than the predetermined value. An automatic-gain-control amplifier receives the output from the amplifier with the limiting function, and amplifies the input voltage signal to a voltage signal having a constant swing.

Abstract: A semiconductor memory has a plurality of word lines a plurality of bit line pairs and a plurality of memory cells formed at intersection points between the word lines and the bit line pairs. A word decoder generates a word line select signal upon receipt of an address signal and a bit decoder generates a bit line select signal on receiving the address signal. A bit line load circuit receives a signal current from the applicable memory cell, a sense circuit detects an output signal from the bit line load circuit, and a bit line pull-down circuit and a bit line recovery circuit drives the applicable bit lines upon writing data to the memory cell in question.

Abstract: Disclosed is a static type memory cell with high immunity from alpha ray-induced soft errors. The memory cell has a coupling capacitance C.sub.c between two data storage nodes 1 and 2. The p-well (or p-substrate) in which the driver-MOS transistors MN3, MN4 and the transfer MOS transistors MN1, MN2 are formed is connected to a V.sub.bb generator. The voltage V.sub.bb is set lower than the low level V.sub.L of the memory cell signal potential. Even when the potential variation .DELTA.V.sub.L of the low-voltage side node 2 is large, the parasitic diode present between the n-type diffusion layer corresponding to the source or drain of MN1-MN4 and the p-well (or p-substrate) does not turn on. Erroneous operations can therefore be prevented.

Abstract: A decoder formed of multiple circuit blocks each including bipolar transistors Q1 and Q2 having their collectors connected to resistors R1 and R2, respectively, a bipolar transistor Q3 having its collector supplied with a power voltage, and a current source I1 connected commonly to the emitters of Q1-Q3. This circuit configuration permits the decoder and BiCMOS memories using it to operate with a low supply voltage.

Abstract: A semiconductor memory device has a primary memory cell array, a primary decoder having a first circuit producing an intermediate signal from an address signal and a second circuit producing a first cell selection signal from the intermediate signal for selectively driving a word line and a bit line, an auxiliary memory cell array having a plurality of memory cells, each being used for a defective memory cell found in the primary memory cell array, an auxiliary decoder connected to the primary decoder to receive the intermediate signal, a non-volatile memory for storing first information indicating that the primary memory cell array contains a defective memory cell from which a cell defect signal is produced and for storing second information indicating an address of the defective memory cell from which a defective cell address signal is produced, and a control circuit responsive to the cell defect signal and the defective cell address signal for producing a first control signal to be supplied to the second c

Abstract: The disclosure includes feeding a current I.sub.R to only BIT lines selected, or feeding current I.sub.R transiently to only the BIT lines switched from unselected to selected states; and a sense amplifier for detecting the difference between the currents flowing in selected BIT lines to read out stored information, wherein current I.sub.R and cell current I.sub.cell have a relation of I.sub.R >I.sub.cell. The BiC MOS memory has high speed, low power and high integration density. Diodes are provided between the memory cell and the BIT lines.

Abstract: A semiconductor circuit having a plurality of circuit blocks, each having latch circuits each one thereof being controlled by an internally provided clock signal for preventing malfunction of the circuit. Each circuit is provided with the latch function so that the cycle time is made shorter than the access time. Moreover, the latch means are driven in such a manner that the adjoining ones are prevented from being put to through-state simultaneously, whereby malfunction is prevented.