Patents by Inventor Kenichi Ohyama
Kenichi Ohyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190173772Abstract: A method of monitoring includes transmitting, by a computer, a polling signal to a first communication apparatus, receiving, from the first communication apparatus, information on a first notification target which is detected in the first communication apparatus and first interval information indicative of a difference between timing at which the first notification item is detected and timing at which the polling signal is received in the first communication apparatus, and determining, based on first time information indicative of timing at which polling is performed and the first interval information, a time sequence of the first notification target and a second notification target which is detected in a second communication apparatus.Type: ApplicationFiled: November 28, 2018Publication date: June 6, 2019Applicant: FUJITSU LIMITEDInventors: Tatsuya Hamachi, Kenichi Ohyama, Yushi Nobayashi
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Patent number: 9742513Abstract: A transmission apparatus configured to extract reception data and a first clock from a received signal and transmit the reception data based on a second clock synchronized with the first clock, the transmission apparatus includes: a detector configured to detect a frequency difference between the first clock and the second clock; a selector configured to select parallel data according to the frequency difference from a plurality of parallel data obtained by shifting bit patterns formed by bits of continuing “0” and continuing “1” by different number of the bits with each other, and a converter configured to convert the parallel data selected by the selector into serial data so as to be the second clock.Type: GrantFiled: May 26, 2016Date of Patent: August 22, 2017Assignee: FUJITSU LIMITEDInventors: Haruhisa Fukano, Kenichi Ohyama, Toshiharu Hirose, Katsuya Kinoshita
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Publication number: 20160373245Abstract: A transmission apparatus configured to extract reception data and a first clock from a received signal and transmit the reception data based on a second clock synchronized with the first clock, the transmission apparatus includes: a detector configured to detect a frequency difference between the first clock and the second clock; a selector configured to select parallel data according to the frequency difference from a plurality of parallel data obtained by shifting bit patterns formed by bits of continuing “0” and continuing “1” by different number of the bits with each other, and a converter configured to convert the parallel data selected by the selector into serial data so as to be the second clock.Type: ApplicationFiled: May 26, 2016Publication date: December 22, 2016Applicant: FUJITSU LIMITEDInventors: Haruhisa Fukano, Kenichi Ohyama, Toshiharu Hirose, Katsuya Kinoshita
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Publication number: 20150256294Abstract: A transmission apparatus includes a detection unit, an error determination unit, a conversion unit, and a deletion unit. The detection unit detects a header in a frame. The error determination unit determines whether or not an error exists in the header detected by the detection unit. The conversion unit converts the frame into a transmission frame to be transmitted to another transmission apparatus when the error determination unit determines that the error exists. The deletion unit deletes the transmission frame.Type: ApplicationFiled: February 5, 2015Publication date: September 10, 2015Inventors: TAKUMI KIKUGAWA, KENICHI OHYAMA, EIJI GOBARU
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Publication number: 20140321851Abstract: A transmission device includes: a detector to detect a head pattern indicating a head of data for each of ports that receives the data; a write controller to write the data to a memory provided for each of the ports, based on a detection timing of the head pattern detected by the detector; a determination unit to determine, among ports for each of which the head pattern has been detected by the detector, a specific port for which a total delay amount is minimum, the total delay amount being a total sum of delay amounts from the head pattern related to the specific port to each of the head patterns related to ports other than the specific port; and a read controller to read the data from the memory, based on the detection timing of the head pattern related to the specific port determined by the determination unit.Type: ApplicationFiled: March 24, 2014Publication date: October 30, 2014Applicant: FUJITSU LIMITEDInventors: Toshiharu HIROSE, Kenichi Ohyama, Akira Hashimoto, Haruhisa Fukano
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Publication number: 20130332629Abstract: A configuration controller configured to control configuration of a partially configurable programmable device, includes a determination unit configured to determine whether or not circuit data to be arranged in any one of a plurality of areas in the programmable device matches desired circuit data for which a desired arrangement target area is specified, before the circuit data to be arranged is written into the programmable device, and a data controller configured to control whether or not the circuit data to be arranged is to be written into the programmable device, in accordance with the determination result of the determination unit.Type: ApplicationFiled: May 2, 2013Publication date: December 12, 2013Applicant: FUJITSU LIMITEDInventors: Katsuyuki OKABE, Koichi KINOSHITA, Kenichi OHYAMA, Haruhisa FUKANO, Yuji SHIMADA
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Patent number: 8196021Abstract: An apparatus for frame transmission includes a dummy data inserting unit that inserts dummy data, at timing of an interval in which a received frame input intermittently is not detected, in a sequence of processing processes of scrambling processing of user data cut out from the received frame, reading-out of the data after the scrambling processing with a parity appended thereto from a memory and parity checking thereof, and descrambling processing of the data after the parity checking, and an error determining unit that determines whether an error is occurring in the sequence of the processing processes, based on the dummy data obtained by the descrambling processing of the dummy data inserted in the sequence of the processing processes by the dummy data inserting unit.Type: GrantFiled: January 29, 2009Date of Patent: June 5, 2012Assignee: Fujitsu LimitedInventors: Katsuyuki Okabe, Toshitsugu Hagio, Kenichi Ohyama
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Publication number: 20090287985Abstract: An apparatus for frame transmission includes a dummy data inserting unit that inserts dummy data, at timing of an interval in which a received frame input intermittently is not detected, in a sequence of processing processes of scrambling processing of user data cut out from the received frame, reading-out of the data after the scrambling processing with a parity appended thereto from a memory and parity checking thereof, and descrambling processing of the data after the parity checking, and an error determining unit that determines whether an error is occurring in the sequence of the processing processes, based on the dummy data obtained by the descrambling processing of the dummy data inserted in the sequence of the processing processes by the dummy data inserting unit.Type: ApplicationFiled: January 29, 2009Publication date: November 19, 2009Applicant: FUJITSU LIMITEDInventors: Katsuyuki Okabe, Toshitsugu Hagio, Kenichi Ohyama
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Publication number: 20080232245Abstract: A transmission apparatus includes an active programmable device; a standby programmable device upgrading the version; an external memory part that includes a table memory and a main signal memory and that is shared between the two programmable devices; and a switching part that selects either of the main signals processed by the two programmable devices to transmit the selected main signal to an output path. The active programmable device is capable of processing the main signals in parallel with the standby programmable device and receives a notification of completion of the version upgrade from the standby programmable device to issue an instruction to start switching to the standby programmable device. The standby programmable device uses the table memory and the main signal memory updated by the active programmable device to process the main signals in response to the instruction to start the switching.Type: ApplicationFiled: March 7, 2008Publication date: September 25, 2008Inventors: Takayuki Furukawa, Kenichi Ohyama, Katsuyuki Okabe, Noboru Kamei
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Publication number: 20080218360Abstract: A transmission apparatus transmitting/receiving data to and from other transmission apparatuses through a network includes a temperature rise detector detecting a temperature rise of the transmission apparatus and a communication controller restricting transmission from the other transmission apparatuses to the transmission apparatus when the temperature rise of the transmission apparatus is detected.Type: ApplicationFiled: February 19, 2008Publication date: September 11, 2008Applicant: Fujitsu LimitedInventors: Koji Nekoda, Kenichi Ohyama, Atsunori Machida
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Publication number: 20080175262Abstract: A data communication apparatus stores each data received via a network and transfers each data in accordance with destination addresses of each data. The data communication apparatus includes a stop-control information generator, which upon updating of circuit configuration information of a programmable logic circuit provided in the data communication apparatus is performed, generates stop-control information stopping data transmitted from an external data communication apparatus from entering the programmable logic circuit.Type: ApplicationFiled: January 14, 2008Publication date: July 24, 2008Applicant: Fujitsu LimitedInventors: Hiroshi KAWANO, Kenichi Ohyama, Katsuyuki Okabe