Patents by Inventor Kenichi Oi

Kenichi Oi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240083518
    Abstract: A floor mat arranged in a working machine includes a floor portion, a wall portion arranged on a circumferential portion of the floor portion, and an opening portion arranged on a part of a connecting portion of the wall portion, the connecting portion connecting to the floor portion. The floor mat includes a mat main body arranged on the floor portion, a covering portion configured to cover the opening portion, and an connecting portion configured to connect the covering portion flexibly to a circumferential portion of the mat main body.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: KUBOTA CORPORATION
    Inventors: Masahiro AIHARA, Shota SAKAMOTO, Akihiro ICHIHARA, Kazuya OI, Yoshiki TAKIZAWA, Kenichi SAIKI
  • Patent number: 7660411
    Abstract: A portable telephone in which two bodies thereof are placed in superposed relation, and one body slides relative to the other body to change how far they superpose, thus expanding and contracting the overall length of the telephone in the sliding direction. The one body can pull out relative to the other body with an area left where a part of the one body is superposed on the other body in the extended state. Engaging members, i.e. engaging pawls and sliders, that serve as a rotation preventing mechanism for preventing the two bodies from relative rotating are intensively provided in the superposed area within the extended state.
    Type: Grant
    Filed: May 31, 2004
    Date of Patent: February 9, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kenichi Oi
  • Patent number: 7312522
    Abstract: A mounting member of a semiconductor device according to the present invention includes a wiring substrate to input and/or output actuating signals to a semiconductor device, a power supplying conductor plate to supply actuating power to the semiconductor device, and the GND conductor plate. The wiring substrate, the power supplying conductor plate, and the GND conductor plate are laminated with insulation films between respective layers. Input/output signals as well as minute driving current is supplied from wiring substrate, and the large main driving current is supplied through the power supplying conductor plate as well as the GND conductor plate.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: December 25, 2007
    Assignee: Espec Corp.
    Inventor: Kenichi Oi
  • Publication number: 20070211889
    Abstract: A portable telephone in which two bodies thereof are placed in superposed relation, and one body slides relative to the other body to change how far they superpose, thus expanding and contracting the overall length of the telephone in the sliding direction. The one body can pull out relative to the other body with an area left where a part of the one body is superposed on the other body in the extended state. Engaging members, i.e. engaging pawls and sliders, that serve as a rotation preventing mechanism for preventing the two bodies from relative rotating are intensively provided in the superposed area within the extended state.
    Type: Application
    Filed: May 31, 2004
    Publication date: September 13, 2007
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kenichi Oi
  • Patent number: 7214961
    Abstract: A semiconductor testing device of the invention has a measuring substrate that is provided with holes therethrough for exposing a pad of each of the dies of a semiconductor wafer mounted on the measuring substrate, the semiconductor wafer being supported by a wafer holder on one side of the measuring substrate, and the other side of the measuring substrate being provided with a wiring pattern for transmitting an evaluation test signal to the semiconductor wafer supported on the measuring substrate. The measuring substrate, with the pad of each of the dies being wire bonded with a pad of the wiring pattern through the holes, are set for an evaluation test so that a mount part of the semiconductor is placed inside a high temperature chamber, and that a terminal part for applying the evaluation test signal is placed outside of the high temperature chamber. As a result, there is provided a semiconductor testing device, inexpensively, that can suitably evaluate a semiconductor under a temperature of about 400° C.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: May 8, 2007
    Assignee: Espec Corp.
    Inventors: Kenichi Oi, Hirotaka Jiten
  • Publication number: 20050133786
    Abstract: A semiconductor testing device of the invention has a measuring substrate that is provided with holes therethrough for exposing a pad of each of the dies of a semiconductor wafer mounted on the measuring substrate, the semiconductor wafer being supported by a wafer holder on one side of the measuring substrate, and the other side of the measuring substrate being provided with a wiring pattern for transmitting an evaluation test signal to the semiconductor wafer supported on the measuring substrate. The measuring substrate, with the pad of each of the dies being wire bonded with a pad of the wiring pattern through the holes, are set for an evaluation test so that a mount part of the semiconductor is placed inside a high temperature chamber, and that a terminal part for applying the evaluation test signal is placed outside of the high temperature chamber. As a result, there is provided a semiconductor testing device, inexpensively, that can suitably evaluate a semiconductor under a temperature of about 400° C.
    Type: Application
    Filed: December 1, 2004
    Publication date: June 23, 2005
    Inventors: Kenichi Oi, Hirotaka Jiten
  • Publication number: 20050116328
    Abstract: A substrate of the present invention includes an electrically-insulating glass layer formed on both sides of a stainless-plate measuring substrate. The substrate also has a wiring pattern on the electrically-insulating glass layer, and an overcoat glass layer covering the wiring pattern. Thus, the present invention provides a substrate that is inexpensive, can withstand a high temperature of about 400° C. in EM evaluations and the like, and can easily be provided in a large size.
    Type: Application
    Filed: December 1, 2004
    Publication date: June 2, 2005
    Inventors: Kenichi Oi, Hirotaka Jiten
  • Publication number: 20050092988
    Abstract: A mounting member of a semiconductor device according to the present invention includes a wiring substrate to input and/or output actuating signals to a semiconductor device, a power supplying conductor plate to supply actuating power to the semiconductor device, and the GND conductor plate. The wiring substrate, the power supplying conductor plate, and the GND conductor plate are laminated with insulation films between respective layers. Input/output signals as well as minute driving current is supplied from wiring substrate, and the large main driving current is supplied through the power supplying conductor plate as well as the GND conductor plate.
    Type: Application
    Filed: October 28, 2004
    Publication date: May 5, 2005
    Inventor: Kenichi Oi
  • Patent number: 5574384
    Abstract: An apparatus for burn-in of semiconductor devices has board assemblies including a burn-in board and a driver board. The burn-in board has sockets on a first surface for accepting the semiconductor devices and first terminals extending from the sockets to protrude from a first back side of the burn-in board. The driver board has a second surface carrying an electronic circuit to drive the semiconductor devices and a second back side with second terminals for connecting the electronic circuit to the first terminals. The driver board has an edge connector with terminals for applying power to the electronic circuit. The burn-in board and the driver board are disposed with the first and second back sides facing such that corresponding ones of the first and second terminal can be brought into and out of contact with each other. The board assemblies are supported in a housing wherein the board assemblies form partitions isolating first and second environmental spaces for burn-in and cooling operation.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: November 12, 1996
    Assignee: Tabai Espec Corp.
    Inventor: Kenichi Oi
  • Patent number: D905638
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 22, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinichi Kato, Kenichi Oi, Toshio Nakayama, Masahiro Ichikawa, Taku Kondo, Koji Uchimura
  • Patent number: D918857
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: May 11, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinichi Kato, Kenichi Oi, Toshio Nakayama, Masahiro Ichikawa, Taku Kondo, Koji Uchimura
  • Patent number: D1016031
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Kato, Yorimasa Yasuda, Satoru Kozuka, Hideaki Yamamoto, Nichika Moriguchi, Keisuke Tada, Kenichi Oi, Masaaki Kadoyanagi, Toshio Nakayama, Shinichiro Ando, Akihiro Gonda
  • Patent number: D1016032
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 27, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Kato, Yorimasa Yasuda, Satoru Kozuka, Hideaki Yamamoto, Nichika Moriguchi, Keisuke Tada, Kenichi Oi, Masaaki Kadoyanagi, Toshio Nakayama, Shinichiro Ando, Akihiro Gonda
  • Patent number: D1016033
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 27, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Kato, Yorimasa Yasuda, Satoru Kozuka, Hideaki Yamamoto, Nichika Moriguchi, Keisuke Tada, Kenichi Oi, Masaaki Kadoyanagi, Toshio Nakayama, Shinichiro Ando, Akihiro Gonda