Patents by Inventor Kenichi Oi
Kenichi Oi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240083518Abstract: A floor mat arranged in a working machine includes a floor portion, a wall portion arranged on a circumferential portion of the floor portion, and an opening portion arranged on a part of a connecting portion of the wall portion, the connecting portion connecting to the floor portion. The floor mat includes a mat main body arranged on the floor portion, a covering portion configured to cover the opening portion, and an connecting portion configured to connect the covering portion flexibly to a circumferential portion of the mat main body.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: KUBOTA CORPORATIONInventors: Masahiro AIHARA, Shota SAKAMOTO, Akihiro ICHIHARA, Kazuya OI, Yoshiki TAKIZAWA, Kenichi SAIKI
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Patent number: 7660411Abstract: A portable telephone in which two bodies thereof are placed in superposed relation, and one body slides relative to the other body to change how far they superpose, thus expanding and contracting the overall length of the telephone in the sliding direction. The one body can pull out relative to the other body with an area left where a part of the one body is superposed on the other body in the extended state. Engaging members, i.e. engaging pawls and sliders, that serve as a rotation preventing mechanism for preventing the two bodies from relative rotating are intensively provided in the superposed area within the extended state.Type: GrantFiled: May 31, 2004Date of Patent: February 9, 2010Assignee: Mitsubishi Electric CorporationInventor: Kenichi Oi
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Patent number: 7312522Abstract: A mounting member of a semiconductor device according to the present invention includes a wiring substrate to input and/or output actuating signals to a semiconductor device, a power supplying conductor plate to supply actuating power to the semiconductor device, and the GND conductor plate. The wiring substrate, the power supplying conductor plate, and the GND conductor plate are laminated with insulation films between respective layers. Input/output signals as well as minute driving current is supplied from wiring substrate, and the large main driving current is supplied through the power supplying conductor plate as well as the GND conductor plate.Type: GrantFiled: October 28, 2004Date of Patent: December 25, 2007Assignee: Espec Corp.Inventor: Kenichi Oi
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Publication number: 20070211889Abstract: A portable telephone in which two bodies thereof are placed in superposed relation, and one body slides relative to the other body to change how far they superpose, thus expanding and contracting the overall length of the telephone in the sliding direction. The one body can pull out relative to the other body with an area left where a part of the one body is superposed on the other body in the extended state. Engaging members, i.e. engaging pawls and sliders, that serve as a rotation preventing mechanism for preventing the two bodies from relative rotating are intensively provided in the superposed area within the extended state.Type: ApplicationFiled: May 31, 2004Publication date: September 13, 2007Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Kenichi Oi
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Patent number: 7214961Abstract: A semiconductor testing device of the invention has a measuring substrate that is provided with holes therethrough for exposing a pad of each of the dies of a semiconductor wafer mounted on the measuring substrate, the semiconductor wafer being supported by a wafer holder on one side of the measuring substrate, and the other side of the measuring substrate being provided with a wiring pattern for transmitting an evaluation test signal to the semiconductor wafer supported on the measuring substrate. The measuring substrate, with the pad of each of the dies being wire bonded with a pad of the wiring pattern through the holes, are set for an evaluation test so that a mount part of the semiconductor is placed inside a high temperature chamber, and that a terminal part for applying the evaluation test signal is placed outside of the high temperature chamber. As a result, there is provided a semiconductor testing device, inexpensively, that can suitably evaluate a semiconductor under a temperature of about 400° C.Type: GrantFiled: December 1, 2004Date of Patent: May 8, 2007Assignee: Espec Corp.Inventors: Kenichi Oi, Hirotaka Jiten
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Publication number: 20050133786Abstract: A semiconductor testing device of the invention has a measuring substrate that is provided with holes therethrough for exposing a pad of each of the dies of a semiconductor wafer mounted on the measuring substrate, the semiconductor wafer being supported by a wafer holder on one side of the measuring substrate, and the other side of the measuring substrate being provided with a wiring pattern for transmitting an evaluation test signal to the semiconductor wafer supported on the measuring substrate. The measuring substrate, with the pad of each of the dies being wire bonded with a pad of the wiring pattern through the holes, are set for an evaluation test so that a mount part of the semiconductor is placed inside a high temperature chamber, and that a terminal part for applying the evaluation test signal is placed outside of the high temperature chamber. As a result, there is provided a semiconductor testing device, inexpensively, that can suitably evaluate a semiconductor under a temperature of about 400° C.Type: ApplicationFiled: December 1, 2004Publication date: June 23, 2005Inventors: Kenichi Oi, Hirotaka Jiten
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Publication number: 20050116328Abstract: A substrate of the present invention includes an electrically-insulating glass layer formed on both sides of a stainless-plate measuring substrate. The substrate also has a wiring pattern on the electrically-insulating glass layer, and an overcoat glass layer covering the wiring pattern. Thus, the present invention provides a substrate that is inexpensive, can withstand a high temperature of about 400° C. in EM evaluations and the like, and can easily be provided in a large size.Type: ApplicationFiled: December 1, 2004Publication date: June 2, 2005Inventors: Kenichi Oi, Hirotaka Jiten
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Publication number: 20050092988Abstract: A mounting member of a semiconductor device according to the present invention includes a wiring substrate to input and/or output actuating signals to a semiconductor device, a power supplying conductor plate to supply actuating power to the semiconductor device, and the GND conductor plate. The wiring substrate, the power supplying conductor plate, and the GND conductor plate are laminated with insulation films between respective layers. Input/output signals as well as minute driving current is supplied from wiring substrate, and the large main driving current is supplied through the power supplying conductor plate as well as the GND conductor plate.Type: ApplicationFiled: October 28, 2004Publication date: May 5, 2005Inventor: Kenichi Oi
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Patent number: 5574384Abstract: An apparatus for burn-in of semiconductor devices has board assemblies including a burn-in board and a driver board. The burn-in board has sockets on a first surface for accepting the semiconductor devices and first terminals extending from the sockets to protrude from a first back side of the burn-in board. The driver board has a second surface carrying an electronic circuit to drive the semiconductor devices and a second back side with second terminals for connecting the electronic circuit to the first terminals. The driver board has an edge connector with terminals for applying power to the electronic circuit. The burn-in board and the driver board are disposed with the first and second back sides facing such that corresponding ones of the first and second terminal can be brought into and out of contact with each other. The board assemblies are supported in a housing wherein the board assemblies form partitions isolating first and second environmental spaces for burn-in and cooling operation.Type: GrantFiled: May 15, 1995Date of Patent: November 12, 1996Assignee: Tabai Espec Corp.Inventor: Kenichi Oi
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Patent number: D905638Type: GrantFiled: June 17, 2019Date of Patent: December 22, 2020Assignee: Mitsubishi Electric CorporationInventors: Shinichi Kato, Kenichi Oi, Toshio Nakayama, Masahiro Ichikawa, Taku Kondo, Koji Uchimura
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Patent number: D918857Type: GrantFiled: June 14, 2019Date of Patent: May 11, 2021Assignee: Mitsubishi Electric CorporationInventors: Shinichi Kato, Kenichi Oi, Toshio Nakayama, Masahiro Ichikawa, Taku Kondo, Koji Uchimura
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Patent number: D1016031Type: GrantFiled: July 14, 2021Date of Patent: February 27, 2024Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Kato, Yorimasa Yasuda, Satoru Kozuka, Hideaki Yamamoto, Nichika Moriguchi, Keisuke Tada, Kenichi Oi, Masaaki Kadoyanagi, Toshio Nakayama, Shinichiro Ando, Akihiro Gonda
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Patent number: D1016032Type: GrantFiled: July 23, 2021Date of Patent: February 27, 2024Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Kato, Yorimasa Yasuda, Satoru Kozuka, Hideaki Yamamoto, Nichika Moriguchi, Keisuke Tada, Kenichi Oi, Masaaki Kadoyanagi, Toshio Nakayama, Shinichiro Ando, Akihiro Gonda
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Patent number: D1016033Type: GrantFiled: July 23, 2021Date of Patent: February 27, 2024Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Kato, Yorimasa Yasuda, Satoru Kozuka, Hideaki Yamamoto, Nichika Moriguchi, Keisuke Tada, Kenichi Oi, Masaaki Kadoyanagi, Toshio Nakayama, Shinichiro Ando, Akihiro Gonda