Patents by Inventor Kenichi Okabe
Kenichi Okabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240015959Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of at least one semiconductor material layer; memory openings vertically extending through the alternating stack; memory opening fill structures; a dielectric material portion contacting sidewalls of the insulating layers of the alternating stack. In one embodiment, a connection via structure can vertically extend through the dielectric material portion, and a metal plate can contact the connection via structure. Alternately or additionally, an integrated via and pad structure may be provided, which includes a conductive via portion vertically extending through the dielectric material portion and a conductive pad portion located on an end of the conductive via portion.Type: ApplicationFiled: July 5, 2022Publication date: January 11, 2024Inventors: Yusuke Yoshida, Teruo Okina, Kenichi Okabe
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Publication number: 20210210504Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers.Type: ApplicationFiled: January 7, 2020Publication date: July 8, 2021Inventors: Yoshitaka OTSU, Kenichi OKABE, Takashi ARAI
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Publication number: 20160254155Abstract: A protection film is formed on a semiconductor substrate. Impurity ions are implanted into the semiconductor substrate through the protection film. The impurity is activated to form an impurity layer. The protection film is removed after forming the impurity layer. The semiconductor substrate of a surface portion of the impurity layer is removed after removing the protection film. A semiconductor layer is epitaxially grown above the semiconductor substrate after removing the semiconductor substrate of the surface portion of the impurity layer.Type: ApplicationFiled: May 13, 2016Publication date: September 1, 2016Inventors: Taiji Ema, Toshifumi Mori, Toshiki Miyake, Kenichi Okabe
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Publication number: 20120108022Abstract: A method of manufacturing a semiconductor device including a stacked gate type nonvolatile memory cell and a p-channel type first transistor, includes: forming a gate insulating film of the first transistor on a semiconductor substrate; forming a tunnel insulating film of the stacked gate type nonvolatile memory cell on the semiconductor substrate; forming a first conductive layer containing an n-type impurity on the tunnel insulating film and the gate insulating film; and implanting p-type impurity ions to a region of the first conductive layer for forming the first transistor to turn the region of the first conductive layer into a p-type region.Type: ApplicationFiled: December 22, 2011Publication date: May 3, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Toru Anezaki, Kenichi Okabe
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Patent number: 8164142Abstract: According to an aspect of an embodiment, a semiconductor device has a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode formed on the gate insulating film, an impurity diffusion region formed in an area of the semiconductor substrate adjacent to the gate electrode to a first depth to the semiconductor substrate, the impurity diffusion region containing impurity, an inert substance containing region formed in the area of the semiconductor substrate to a second depth deeper than the first depth, the inert substance containing region containing an inert substance, and a diffusion suppressing region formed in the area of the semiconductor substrate to a third depth deeper than the second depth, the diffusion suppressing region containing a diffusion suppressing substance suppressing diffusion of the impurity.Type: GrantFiled: January 4, 2011Date of Patent: April 24, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Kenichi Okabe
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Publication number: 20120083087Abstract: A protection film is formed on a semiconductor substrate. Impurity ions are implanted into the semiconductor substrate through the protection film. The impurity is activated to form an impurity layer. The protection film is removed after forming the impurity layer. The semiconductor substrate of a surface portion of the impurity layer is removed after removing the protection film. A semiconductor layer is epitaxially grown above the semiconductor substrate after removing the semiconductor substrate of the surface portion of the impurity layer.Type: ApplicationFiled: June 29, 2011Publication date: April 5, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Toshifumi Mori, Toshiki Miyake, Kenichi Okabe
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Patent number: 8084338Abstract: The depletion of a gate electrode (103) is suppressed in such a way that impurities are introduced into the gate electrode that is formed on a semiconductor substrate (101), with a gate insulating film (102) interposed between the gate electrode (103) and the semiconductor substrate (101), and that, by irradiating a laser beam onto the gate electrode (103), the introduced impurities are made to diffuse up to the interface between the gate electrode (103) and the gate insulating film (102).Type: GrantFiled: June 20, 2005Date of Patent: December 27, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tomonari Yamamoto, Kenichi Okabe
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Patent number: 7966842Abstract: The refrigerator includes a vegetable compartment (107) thermally insulated by a rear partition (111), and a mist generation department (139) for atomizing a mist into the vegetable compartment (107), and the mist generation department (139) includes a atomizing electrode (135) for atomizing the mist into the vegetable compartment (107), a voltage applicator (133) for applying a voltage to the atomizing electrode (135), and a cooling pin (134) coupled to the atomizing electrode (135), in which the atomizing electrode (135) is cooled to a temperature lower than the dew point by a outlet air-duct for freezer compartment (141), and the moisture in the air is cooled to condense dew on the atomizing electrode (135), and is atomized as a mist into the vegetable compartment (107), and dew can be condensed from moisture onto the atomizing electrode (135) stably and in a simple configuration, and the freshness of the food is enhanced while the reliability of the refrigerator is enhanced.Type: GrantFiled: October 22, 2009Date of Patent: June 28, 2011Assignee: Panasonic CorporationInventors: Toyoshi Kamisako, Yoshihiro Ueda, Kazuya Nakanishi, Tadashi Adachi, Kazuyuki Hamada, Kiyotaka Tabira, Yasuyuki Okamoto, Kenichi Okabe, Masashi Yuasa, Kenichi Kakita, Kiyoshi Mori, Tosiaki Mamemoto, Katsunori Horii
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Patent number: 7939706Abstract: In a urine receptacle of an automatic urine disposal device, a urine backflow prevention sheet, with no water permeability, having funnel-shaped pores, is placed between a top sheet and a urine absorbing sheet. A pair of rectangular electrodes, constituting a urine detection sensor, is glued onto an electrode support sheet and is placed between the top sheet and the urine backflow prevention sheet. A plurality of funnel-shaped pores is formed on the urine backflow prevention sheet.Type: GrantFiled: October 10, 2007Date of Patent: May 10, 2011Assignees: Hitachi, Ltd., Uni-Charm CorporationInventors: Kenichi Okabe, Junichi Kobayashi, Shigeru Machida, Ryousuke Miyagawa, Yoshikazu Ishitsuka, Ichiro Wada, Miou Suzuki
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Publication number: 20110101428Abstract: According to an aspect of an embodiment, a semiconductor device has a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode formed on the gate insulating film, an impurity diffusion region formed in an area of the semiconductor substrate adjacent to the gate electrode to a first depth to the semiconductor substrate, the impurity diffusion region containing impurity, an inert substance containing region formed in the area of the semiconductor substrate to a second depth deeper than the first depth, the inert substance containing region containing an inert substance, and a diffusion suppressing region formed in the area of the semiconductor substrate to a third depth deeper than the second depth, the diffusion suppressing region containing a diffusion suppressing substance suppressing diffusion of the impurity.Type: ApplicationFiled: January 4, 2011Publication date: May 5, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Kenichi Okabe
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Patent number: 7892933Abstract: According to an aspect of an embodiment, a semiconductor device has a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode formed on the gate insulating film, an impurity diffusion region formed in an area of the semiconductor substrate adjacent to the gate electrode to a first depth to the semiconductor substrate, the impurity diffusion region containing impurity, an inert substance containing region formed in the area of the semiconductor substrate to a second depth deeper than the first depth, the inert substance containing region containing an inert substance, and a diffusion suppressing region formed in the area of the semiconductor substrate to a third depth deeper than the second depth, the diffusion suppressing region containing a diffusion suppressing substance suppressing diffusion of the impurity.Type: GrantFiled: July 11, 2008Date of Patent: February 22, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Kenichi Okabe
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Patent number: 7883960Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer.Type: GrantFiled: March 24, 2009Date of Patent: February 8, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Masatoshi Fukuda, Akiyoshi Hatada, Katsuaki Ookoshi, Kenichi Okabe, Tomonari Yamamoto
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Patent number: 7838401Abstract: A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.Type: GrantFiled: August 31, 2009Date of Patent: November 23, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Hiroyuki Ohta, Kenichi Okabe
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Patent number: 7749205Abstract: A wearer wears a urine receptacle in which a urine absorbent material 3 is housed in a substantially rectangular, non-breathable, liquid-impermeable outer sheet having a U-shaped cross-section, and the surface of the urine absorbent material is covered with a hard-breathable, liquid permeable top sheet. Urine is discharged from a urine drainage port formed on the bottom surface of the outer sheet to a sealed urine tank by a vacuum pump through urine drainage tubes.Type: GrantFiled: March 10, 2004Date of Patent: July 6, 2010Assignees: Hitachi, Ltd., Uni-Charm CorporationInventors: Wataru Tazoe, Junichi Kobayashi, Ryousuke Miyagawa, Kenji Yoshida, Shigeru Machida, Ichiro Wada, Miou Suzuki, Kenichi Okabe
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Publication number: 20100077791Abstract: The refrigerator includes a vegetable compartment (107) thermally insulated by a rear partition (111), and a mist generation department (139) for atomizing a mist into the vegetable compartment (107), and the mist generation department (139) includes a atomizing electrode (135) for atomizing the mist into the vegetable compartment (107), a voltage applicator (133) for applying a voltage to the atomizing electrode (135), and a cooling pin (134) coupled to the atomizing electrode (135), in which the atomizing electrode (135) is cooled to a temperature lower than the dew point by a outlet air-duct for freezer compartment (141), and the moisture in the air is cooled to condense dew on the atomizing electrode (135), and is atomized as a mist into the vegetable compartment (107), and dew can be condensed from moisture onto the atomizing electrode (135) stably and in a simple configuration, and the freshness of the food is enhanced while the reliability of the refrigerator is enhanced.Type: ApplicationFiled: October 22, 2009Publication date: April 1, 2010Applicant: Panasonic CorporationInventors: Toyoshi Kamisako, Yoshihiro Ueda, Kazuya Nakanishi, Tadashi Adachi, Kazuyuki Hamada, Kiyotaka Tabira, Yasuyuki Okamoto, Kenichi Okabe, Masashi Yuasa, Kenichi Kakita, Kiyoshi Mori, Tosiaki Mamemoto, Katsunori Horii
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Publication number: 20100077770Abstract: The refrigerator includes a vegetable compartment (107) thermally insulated by a rear partition (111), and a mist generation department (139) for atomizing a mist into the vegetable compartment (107), and the mist generation department (139) includes a atomizing electrode (135) for atomizing the mist into the vegetable compartment (107), a voltage applicator (133) for applying a voltage to the atomizing electrode (135), and a cooling pin (134) coupled to the atomizing electrode (135), in which the atomizing electrode (135) is cooled to a temperature lower than the dew point by a outlet air-duct for freezer compartment (141), and the moisture in the air is cooled to condense dew on the atomizing electrode (135), and is atomized as a mist into the vegetable compartment (107), and dew can be condensed from moisture onto the atomizing electrode (135) stably and in a simple configuration, and the freshness of the food is enhanced while the reliability of the refrigerator is enhanced.Type: ApplicationFiled: October 22, 2009Publication date: April 1, 2010Applicant: Panasonic CorporationInventors: Toyoshi Kamisako, Yoshihiro Ueda, Kazuya Nakanishi, Tadashi Adachi, Kazuyuki Hamada, Kiyotaka Tabira, Yasuyuki Okamoto, Kenichi Okabe, Masashi Yuasa, Kenichi Kakita, Kiyoshi Mori, Tosiaki Mamemoto, Katsunori Horii
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Publication number: 20100024462Abstract: The refrigerator includes a vegetable compartment (107) thermally insulated by a rear partition (111), and a mist generation department (139) for atomizing a mist into the vegetable compartment (107), and the mist generation department (139) includes a atomizing electrode (135) for atomizing the mist into the vegetable compartment (107), a voltage applicator (133) for applying a voltage to the atomizing electrode (135), and a cooling pin (134) coupled to the atomizing electrode (135), in which the atomizing electrode (135) is cooled to a temperature lower than the dew point by a outlet air-duct for freezer compartment (141), and the moisture in the air is cooled to condense dew on the atomizing electrode (135), and is atomized as a mist into the vegetable compartment (107), and dew can be condensed from moisture onto the atomizing electrode (135) stably and in a simple configuration, and the freshness of the food is enhanced while the reliability of the refrigerator is enhanced.Type: ApplicationFiled: October 16, 2009Publication date: February 4, 2010Applicant: Panasonic CorporationInventors: Toyoshi Kamisako, Yoshihiro Ueda, Kazuya Nakanishi, Tadashi Adachi, Kazuyuki Hamada, Kiyotaka Tabira, Yasuyuki Okamoto, Kenichi Okabe, Masashi Yuasa, Kenichi Kakita, Kiyoshi Mori, Tosiaki Mamemoto, Katsunori Horii
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Patent number: 7645665Abstract: A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the semiconductor device; (c) after the steps (a) and (b) are performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of the semiconductor substrate into which ions were implanted; and (d) after the step (c) is performed, executing second annealing with a heating time longer than the heating time of the first annealing, relative to the region of the semiconductor substrate into which ions were implanted. The method for manufacturing a semiconductor device is provided which can dope boron (B) shallowly and at a high concentration.Type: GrantFiled: December 4, 2006Date of Patent: January 12, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Tomohiro Kubo, Kenichi Okabe, Tomonari Yamamoto
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Publication number: 20100003798Abstract: A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.Type: ApplicationFiled: August 31, 2009Publication date: January 7, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroyuki OHTA, Kenichi OKABE
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Publication number: 20090311838Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer.Type: ApplicationFiled: March 24, 2009Publication date: December 17, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Masatoshi FUKUDA, Akiyoshi HATADA, Katsuaki OOKOSHI, Kenichi OKABE, Tomonari YAMAMOTO