Patents by Inventor Ken-ichi Oki
Ken-ichi Oki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6338990Abstract: To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200° C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200° C. or lower.Type: GrantFiled: October 23, 1998Date of Patent: January 15, 2002Assignee: Fujitsu LimitedInventors: Ken-ichi Yanai, Tsutomu Tanaka, Koji Ohgata, Yutaka Takizawa, Ken-ichi Oki, Takuya Hirano
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Patent number: 6130456Abstract: A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode.Type: GrantFiled: October 22, 1997Date of Patent: October 10, 2000Assignee: Fujitsu LimitedInventors: Ken-ichi Oki, Ken-ichi Yanai, Tamotsu Wada, Koji Ohgata, Yutaka Takizawa, Masahiro Okabe, Tsutomu Tanaka
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Patent number: 5994173Abstract: A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode.Type: GrantFiled: September 26, 1997Date of Patent: November 30, 1999Assignee: Fujitsu LimitedInventors: Ken-ichi Oki, Ken-ichi Yanai, Tamotsu Wada, Koji Ohgata, Yutaka Takizawa, Masahiro Okabe, Tsutomu Tanaka
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Patent number: 5879973Abstract: To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200.degree. C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200.degree. C. or lower.Type: GrantFiled: August 2, 1995Date of Patent: March 9, 1999Assignee: Fujitsu LimitedInventors: Ken-ichi Yanai, Tsutomu Tanaka, Koji Ohgata, Yutaka Takizawa, Ken-ichi Oki, Takuya Hirano
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Patent number: 5728592Abstract: A thin film transistor matrix device is fabricated by forming a transparent conductor film and a metal film on an insulating substrate in this order. The metal film and the transparent conductor film are together patterned to form picture element electrodes, and drain bus lines or gate bus lines. Source electrodes and drain electrodes may also be formed from the transparent conductor film and metal film. A semiconductor layer, an insulating film and a conductor film may be formed on the entire surface in this order. In this case, the conductor film, the insulator film and the semiconductor layer are patterned to form an active layer from the semiconductor layer, gate insulating films from the insulating film, and gate electrodes and gate bus lines from the conductor film. By patterning the conductor film, the insulating film and the semiconductor layer, the metal film of the picture element electrodes and drain bus lines is exposed.Type: GrantFiled: July 6, 1995Date of Patent: March 17, 1998Assignee: Fujitsu Ltd.Inventors: Ken-ichi Oki, Ken-ichi Yanai, Tamotsu Wada, Koji Ohgata, Yutaka Takizawa, Masahiro Okabe, Tsutomu Tanaka
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Patent number: 5518940Abstract: A method of manufacturing a semiconductor device according to the present invention includes a process of introducing impurities into a semiconductor layer with a gate electrode and a resist film as a mask after a resist film is formed on the top and the side of the gate electrode by soaking the gate electrode on a semiconductor layer in an electrolyte containing resist and applying voltage to the gate electrode.Type: GrantFiled: January 5, 1995Date of Patent: May 21, 1996Assignee: Fujitsu LimitedInventors: Mari Hodate, Norihisa Matsumoto, Kohji Ohgata, Tamotsu Wada, Ken-iti Yanai, Ken-ichi Oki, Yasuyoshi Mishima, Michiko Takei, Tatsuya Kakehi, Masahiro Okabe
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Patent number: 5470768Abstract: To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200.degree. C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200.degree. C. or lower.Type: GrantFiled: August 5, 1993Date of Patent: November 28, 1995Assignee: Fujitsu LimitedInventors: Ken-ichi Yanai, Tsutomu Tanaka, Koji Ohgata, Yutaka Takizawa, Ken-ichi Oki, Takuya Hirano
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Patent number: 5408252Abstract: In an active matrix-type display device, two pixel electrodes of cells neighboring in the direction of scan bus lines are connected to the same data bus line, and these two cells are independently controlled by the time division technique. When an address pulse is applied to the scan bus line for accessing each cell of the pixel rows, a compensation pulse is applied to the scan bus line arranged on the other side of the pixel row.Type: GrantFiled: May 12, 1994Date of Patent: April 18, 1995Assignee: Fujitsu LimitedInventors: Ken-ichi Oki, Ken-ichi Yanai
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Patent number: 4818981Abstract: An active matrix display device of an improved and simplified configuration and a driving method for the same are disclosed. The display device according to the present invention is characterized in that data bus lines and scan bus lines are separately formed on first and second transparent substrates respectively and the drain electrode of each TFT on the second substrate is connected to the scan bus line to be addressed next. This configuration eliminates earth bus lines of the prior art. This arrangement has effects of simplifying a bus line design and obtaining a higher yield and an increased opening rate for each display element. In order to drive the above device, an address pulse having a stepped waveform is used. Each address pulse has Vgon, Vgc, and Vgoff levels, and a width of two horizontal scan time.Type: GrantFiled: September 11, 1987Date of Patent: April 4, 1989Assignee: Fujitsu LimitedInventors: Ken-ichi Oki, Satoru Kawai, Ken-ichi Yanai, Kazuhiro Takahara