Patents by Inventor Kenichi Ootsuka

Kenichi Ootsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105646
    Abstract: According to one embodiment, an isolator includes a first electrode, a second electrode, a conductive body, and a first insulating layer. The second electrode is provided on the first electrode and separated from the first electrode. The conductive body is provided around the first and second electrodes along a first plane perpendicular to a first direction. The first direction is from the first electrode toward the second electrode. The first insulating layer is provided on the second electrode. The first insulating layer includes silicon, carbon, and nitrogen.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Inventors: Kenichi Ootsuka, Mari Ootsuka
  • Patent number: 11876058
    Abstract: According to one embodiment, an isolator includes a first electrode, a second electrode, a conductive body, and a first insulating layer. The second electrode is provided on the first electrode and separated from the first electrode. The conductive body is provided around the first and second electrodes along a first plane perpendicular to a first direction. The first direction is from the first electrode toward the second electrode. The first insulating layer is provided on the second electrode. The first insulating layer includes silicon, carbon, and nitrogen.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: January 16, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kenichi Ootsuka, Mari Ootsuka
  • Publication number: 20230092162
    Abstract: An insulating device includes: a first inductor including a first coil layer located in a first plane; a second inductor separated from the first inductor, the second inductor including a second coil layer located in the first plane, a central axis of the second coil layer being positioned inside the first coil layer; and an insulating layer located between the first inductor and the second inductor.
    Type: Application
    Filed: March 4, 2022
    Publication date: March 23, 2023
    Inventors: Tatsuya OHGURO, Kenichi OOTSUKA, Mari OTSUKA, Akira ISHIGURO, Masaki YAMADA
  • Patent number: 11405241
    Abstract: According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: August 2, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsuya Ohguro, Tatsuhiro Oda, Kenichi Ootsuka
  • Publication number: 20210305179
    Abstract: According to one embodiment, an isolator includes a first electrode, a second electrode, a conductive body, and a first insulating layer. The second electrode is provided on the first electrode and separated from the first electrode. The conductive body is provided around the first and second electrodes along a first plane perpendicular to a first direction. The first direction is from the first electrode toward the second electrode. The first insulating layer is provided on the second electrode. The first insulating layer includes silicon, carbon, and nitrogen.
    Type: Application
    Filed: September 10, 2020
    Publication date: September 30, 2021
    Inventors: Kenichi Ootsuka, Mari Ootsuka
  • Publication number: 20210266199
    Abstract: According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.
    Type: Application
    Filed: May 12, 2021
    Publication date: August 26, 2021
    Inventors: Tatsuya Ohguro, Tatsuhiro Oda, Kenichi Ootsuka
  • Patent number: 11038721
    Abstract: According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: June 15, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tatsuya Ohguro, Tatsuhiro Oda, Kenichi Ootsuka
  • Publication number: 20210083908
    Abstract: According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.
    Type: Application
    Filed: March 11, 2020
    Publication date: March 18, 2021
    Inventors: Tatsuya Ohguro, Tatsuhiro Oda, Kenichi Ootsuka
  • Publication number: 20160348238
    Abstract: A film forming apparatus according to an embodiment comprises a film forming chamber. A first pipe part is connected to the film forming chamber and leads a discharge gas out of the film forming chamber. The first pipe part has a first opening area in a cross-section perpendicular to a moving direction of the discharge gas. A liquid discharger discharges a part of the discharge gas liquefied in the first pipe part. A second pipe part is provided between the first pipe part and the liquid discharger and has a second opening area smaller than the first opening area in a cross-section perpendicular to a moving direction of the discharge gas.
    Type: Application
    Filed: February 1, 2016
    Publication date: December 1, 2016
    Inventors: Rempei Nakata, Kenichi Ootsuka, Yuuichi Kuroda, Masaki Hirano, Naoto Miyashita, Tsutomu Miki
  • Patent number: 8993440
    Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Masuda, Kei Watanabe, Kenichi Ootsuka
  • Patent number: 8735859
    Abstract: A nonvolatile semiconductor memory device includes: a first interconnect; a second interconnect at a position opposing the first interconnect; and a variable resistance layer between the first interconnect and the second interconnect, the variable resistance layer being capable of reversibly changing between a first state and a second state by a voltage applied via the first interconnect and the second interconnect or a current supplied via the first interconnect and the second interconnect, the first state having a first resistivity, the second state having a second resistivity higher than the first resistivity. Wherein the variable resistance layer has a compound of carbon and silicon as a main component and including hydrogen.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Kuboi, Masayuki Takata, Tsukasa Nakai, Hiroyuki Fukumizu, Yasuhiro Nojiri, Kenichi Ootsuka
  • Publication number: 20130309866
    Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.
    Type: Application
    Filed: July 23, 2013
    Publication date: November 21, 2013
    Inventors: Hideaki Masuda, Kei Watanabe, Kenichi Ootsuka
  • Publication number: 20120273743
    Abstract: A nonvolatile semiconductor memory device includes: a first interconnect; a second interconnect at a position opposing the first interconnect; and a variable resistance layer between the first interconnect and the second interconnect, the variable resistance layer being capable of reversibly changing between a first state and a second state by a voltage applied via the first interconnect and the second interconnect or a current supplied via the first interconnect and the second interconnect, the first state having a first resistivity, the second state having a second resistivity higher than the first resistivity. Wherein the variable resistance layer has a compound of carbon and silicon as a main component and including hydrogen.
    Type: Application
    Filed: November 29, 2010
    Publication date: November 1, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Kuboi, Masayuki Takata, Tsukasa Nakai, Hiroyuki Fukumizu, Yasuhiro Nojiri, Kenichi Ootsuka
  • Publication number: 20100311240
    Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.
    Type: Application
    Filed: March 17, 2010
    Publication date: December 9, 2010
    Inventors: Hideaki Masuda, Kei Watanabe, Kenichi Ootsuka
  • Patent number: 7829898
    Abstract: In a MOSFET using SiC a p-type channel is formed by epitaxial growth, so that the depletion layer produced in the p-type region right under the channel is reduced, even when the device is formed in a self-aligned manner. Thus, a high breakdown voltage is obtained. Also, since the device is formed in a self-aligned manner, the device size can be reduced so that an increased number of devices can be fabricated in a certain area and the on-state resistance can be reduced.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: November 9, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Ootsuka, Tetsuya Takami, Tadaharu Minato
  • Publication number: 20090020834
    Abstract: In a MOSFET using SiC a p-type channel is formed by epitaxial growth, so that the depletion layer produced in the p-type region right under the channel is reduced, even when the device is formed in a self-aligned manner. Thus, a high breakdown voltage is obtained. Also, since the device is formed in a self-aligned manner, the device size can be reduced so that an increased number of devices can be fabricated in a certain area and the on-state resistance can be reduced.
    Type: Application
    Filed: February 14, 2006
    Publication date: January 22, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kenichi Ootsuka, Tetsuya Takami, Tadaharu Minato
  • Patent number: 6530336
    Abstract: A watercraft has a mid-deck storage compartment. The storage compartment is mounted between a forward portion of the seat and a control mast. The storage compartment inclines rearward and partially overhangs an access opening into an engine compartment that is disposed beneath the seat. A box that is detachably connected to a deck of the watercraft defines the compartment. A cup holder can be disposed within the compartment with storage areas being defined around the cup holder and any cup or can that might be secured by the cup holder. The compartment also expands laterally as it increases in depth.
    Type: Grant
    Filed: November 7, 2001
    Date of Patent: March 11, 2003
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventors: Toshiaki Ibata, Kenichi Ootsuka, Akira Nakatsuji, Toshiyuki Hattori
  • Publication number: 20020053308
    Abstract: A watercraft has a mid-deck storage compartment. The storage compartment is mounted between a forward portion of the seat and a control mast. The storage compartment inclines rearward and partially overhangs an access opening into an engine compartment that is disposed beneath the seat. A box that is detachably connected to a deck of the watercraft defines the compartment. A cup holder can be disposed within the compartment with storage areas being defined around the cup holder and any cup or can that might be secured by the cup holder. The compartment also expands laterally as it increases in depth.
    Type: Application
    Filed: November 7, 2001
    Publication date: May 9, 2002
    Inventors: Toshiaki Ibata, Kenichi Ootsuka, Akira Nakatsuji, Toshiyuki Hattori
  • Publication number: 20020053310
    Abstract: A watercraft has an improved bow hatch design. The bow hatch is disposed above a bow storage compartment and can be secured in a closed position. A locking mechanism is provided to maintain the bow hatch in a closed position. The locking mechanism comprises a separated actuator and locking member. Thus, the actuator can be disposed in a location convenient to the operator while the locking member can be mounted in an aesthetically acceptable location. The locking member is mounted rearward of the storage bin and the actuator is located to one side of the steering mast. In addition, a cable extends between the actuator and the locking member. Body panels of the watercraft substantially enclose the cable.
    Type: Application
    Filed: November 7, 2001
    Publication date: May 9, 2002
    Inventors: Toshiaki Ibata, Kenichi Ootsuka, Akira Nakatsuji, Toshiyuki Hattori
  • Publication number: 20020055308
    Abstract: A watercraft has a number of fuel tank-related structures that are designed to either limit the inflow of water into the fuel tank or to enable the removal of water from the fuel tank. A water pool is formed in a portion of the fuel tank with a hose-accepting opening positioned above the water pool such that a siphon can be use to periodically remove water from the fuel supply. An embedded fastener construction also is used to limit the number of openings between the inside and outside of the fuel tank that would need to be sealed to prevent water inflow. A water repellant filter also is used to reduce the likelihood that water can enter the fuel system through a vapor/pressure relief system.
    Type: Application
    Filed: November 7, 2001
    Publication date: May 9, 2002
    Inventors: Toshiaki Ibata, Kenichi Ootsuka, Akira Nakatsuji, Toshiyuki Hattori