Abstract: A semiconductor integrated circuit device is comprised a main memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, the sub memory portion being constituted with a plurality of memory cell groups, and a plurality of registers provided such that different data input/output modes are set independently for the plurality of the memory cell groups. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: This single phase rectification apparatus connects a full wave rectification circuitry (3) to a single phase A.C. power source (1) through a reactor (2), connects a pair of smoothing diodes (5) which is connected in series to one another between the output terminals of the full wave rectification circuitry (3), connects a series connection circuitry of a pair of diodes (4) in parallel to the series connection circuitry (5) of the pair of the smoothing diodes, connects the center point of the pair of the diodes (4) and the center point of the pair of the smoothing diodes (5) to one another, and connects an A.C. capacitor (6) between one input terminal of the full wave rectification circuitry (3) and the center point of the pair of the smoothing diodes (5), so that decrease in size and in cost are realized for the single phase rectification apparatus in its entirety.

Abstract: According to one embodiment, a semiconductor memory (100) can include a firststage control circuit (106) that generates a first stage control signal &phgr;0, a data input/output (DQ) control circuit (116) that generates a DQ control signal &phgr;1 based on the first stage control signal &phgr;0 and a row address enable signal RASE, and a data mask (DQM) control circuit (114) that generates a DQM control signal &phgr;2 based on the first stage control signal &phgr;0, row address enable signal RASE, and a column address strobe (CAS) latency equal to one value (CLT1). A DQ first-stage circuit (112) is coupled to the DQ control circuit (116) and a DQM first-stage circuit (110) is coupled to the DQM control circuit (116). The DQ and DQM first-stage circuits (110 and 112) can be deactivated when the RASE signal, CASE signals are inactive and the CAS latency is greater than one.

Abstract: A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion constructed with memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion constructed with a plurality of memory cells arranged in a plurality of rows and in a plurality of columns and a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, wherein the data transfer bus lines in a memory cell area of the main memory portion are arranged in parallel to bit lines in a column direction and connected to the bit lines through a column selection circuit. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion, a sub memory portion composed of a plurality of memory cell groups and a bi-directional data transfer circuit provided between the main memory portion and the sub memory portion, wherein power source voltages of the main memory portion and the sub memory portion are different from each other. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: Control signals for refreshing interval selection is simplified and yield in production of a dynamic memory device is improved by a dynamic memory device of the invention.

Abstract: A dynamic random access memory device enters into a self-refresh mode in response to a CAS-before-RAS sequence, and a controller incorporated in the dynamic random access memory device deactivates a column addressing system and a data output system in the self-refresh mode for decreasing a current consumption, wherein the controller is responsive to an external test control signal for temporally activating the column addressing system and the data output system, and a self-refresh cycle time is directly measured at a data output pin.

Abstract: A DRAM incorporated with a self-refresh circuit is disclosed which includes at least one terminal (bonding pad) optionally supplied with a first or a second potential level, a row address buffer/decoder having an input node coupled to the terminal to receive the potential level thereof and energizing a first number of word lines when the input node is at the first potential level and a second number of word lines when the input node is at the second potential level, a gate circuit inserted between the terminal and the input node of the address buffer/decoder and activated in the self-refresh mode to hold the input node at the first potential irrespective of the potential level of the terminal, a refresh timer activated in the slef-refresh mode for generating a refresh request signal in a predetermined cycle, and a refresh controller responding to the refresh request and refreshing memory cells connected to the energized first number of word lines.