Patents by Inventor Kenichi Satori
Kenichi Satori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8468273Abstract: An information storage apparatus transmits or receives information to or from another information processing apparatus in one of a plurality of data transfer modes. The information storage apparatus includes first storage means for storing the information; information transmission/reception control means for controlling transmission or reception of the information between the first storage means and second storage means contained in the other information processing apparatus; command analysis means for analyzing a command supplied from the other information processing apparatus to determine which of the plurality of data transfer modes should be applied; and configuration means for configuring the information transmission/reception control means based on a result of determination of the data transfer mode by the command analysis means.Type: GrantFiled: June 21, 2007Date of Patent: June 18, 2013Assignee: Sony CorporationInventors: Naohiro Adachi, Kenichi Satori, Kenichi Nakanishi, Tamaki Konno, Junko Nagata
-
Patent number: 8271696Abstract: A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.Type: GrantFiled: October 28, 2011Date of Patent: September 18, 2012Assignee: Sony CorporationInventors: Tamaki Konno, Kenichi Satori, Junko Nagata, Noriyuki Hosoe, Naohiro Adachi, Kenichi Nakanishi
-
Publication number: 20120047290Abstract: A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.Type: ApplicationFiled: October 28, 2011Publication date: February 23, 2012Applicant: Sony CorporationInventors: Tamaki Konno, Kenichi Satori, Junko Nagata, Noriyuki Hosoe, Naohiro Adachi, Kenichi Nakanishi
-
Patent number: 8073987Abstract: A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.Type: GrantFiled: November 18, 2010Date of Patent: December 6, 2011Assignee: Sony CorporationInventors: Tamaki Konno, Kenichi Satori, Junko Nagata, Noriyuki Hosoe, Naohiro Adachi, Kenichi Nakanishi
-
Publication number: 20110078338Abstract: A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.Type: ApplicationFiled: November 18, 2010Publication date: March 31, 2011Applicant: SONY CORPORATIONInventors: Tamaki Konno, Kenichi Satori, Junko Nagata, Noriyuki Hosoe, Naohiro Adachi, Kenichi Nakanishi
-
Patent number: 7865628Abstract: A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.Type: GrantFiled: July 2, 2007Date of Patent: January 4, 2011Assignee: Sony CorporationInventors: Tamaki Konno, Kenichi Satori, Junko Nagata, Noriyuki Hosoe, Naohiro Adachi, Kenichi Nakanishi
-
Patent number: 7836263Abstract: A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.Type: GrantFiled: February 2, 2005Date of Patent: November 16, 2010Assignee: Sony CorporationInventors: Takahiro Fukushige, Kenichi Satori, Kenichi Nakanishi, Hideaki Bando, Junko Sasaki, Kunihiko Miura, Toshinori Nakamura, Kensuke Hatsukawa
-
Patent number: 7530005Abstract: The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage device 1, when data read processing is performed for the erase-processing applied area in a memory section 2 to read out erase-state actual data Ddr and erase-state parity data Ddp each containing only “1s”, the erase-state actual data Ddr and erase-state parity data Ddp are inverted by a third data inverting circuit 13 to make all the values thereof “0”, followed by execution of the error detection processing. With the above configuration, it is possible to prevent an error from being detected in the error detection processing.Type: GrantFiled: September 8, 2005Date of Patent: May 5, 2009Assignee: Sony CorporationInventors: Kenichi Satori, Kenichi Nakanishi, Hideaki Bando, Takahiro Fukushige
-
Patent number: 7325104Abstract: A storage device includes a plurality of memories storing data; and a controller controlling the memories, the controller performing in parallel in a number of the memories, the number being specified by a supplied specifying signal, one of a data writing process for writing data supplied from a connection destination device to which the storage device is connectable and a data reading process for reading data requested by the connection destination device.Type: GrantFiled: January 11, 2006Date of Patent: January 29, 2008Assignee: Sony CorporationInventors: Kenichi Satori, Keiichi Tsutsui, Kenichi Nakanishi, Hideaki Bando, Hideaki Okubo, Yoshitaka Aoki, Tamaki Konno
-
Publication number: 20080022018Abstract: A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.Type: ApplicationFiled: July 2, 2007Publication date: January 24, 2008Applicant: Sony CorporationInventors: Tamaki Konno, Kenichi Satori, Junko Nagata, Noriyuki Hosoe, Naohiro Adachi, Kenichi Nakanishi
-
Publication number: 20080016291Abstract: An information storage apparatus transmits or receives information to or from another information processing apparatus in one of a plurality of data transfer modes. The information storage apparatus includes first storage means for storing the information; information transmission/reception control means for controlling transmission or reception of the information between the first storage means and second storage means contained in the other information processing apparatus; command analysis means for analyzing a command supplied from the other information processing apparatus to determine which of the plurality of data transfer modes should be applied; and configuration means for configuring the information transmission/reception control means based on a result of determination of the data transfer mode by the command analysis means.Type: ApplicationFiled: June 21, 2007Publication date: January 17, 2008Inventors: Naohiro Adachi, Kenichi Satori, Kenichi Nakanishi, Tamaki Konno, Junko Nagata
-
Publication number: 20070143534Abstract: A nonvolatile-memory-access control apparatus controls operations for accessing a nonvolatile memory, which include plural cycles by a processing device. The nonvolatile-memory-access control apparatus includes a nonvolatile-memory-access-operation control unit that is capable of setting information on a series of nonvolatile-memory-access operations of the plural cycles, and when a request for access to the nonvolatile memory is received from the processing device, the unit is capable of controlling a series of operations for accessing the nonvolatile memory on the basis of the information set.Type: ApplicationFiled: December 4, 2006Publication date: June 21, 2007Applicant: Sony CorporationInventors: Takuya Hashimoto, Kunihiro Miura, Toshinori Nakamura, Hideo Nomura, Kenichi Satori, Kenichi Nakanishi, Naohiro Adachi, Tamaki Konno
-
Patent number: 7233541Abstract: The present invention is intended to significantly enhance processing efficiency. The card-type semiconductor storage device has a first data communication line group for connecting nonvolatile memories in a first port to a controller block and a second data communication line group for connecting nonvolatile memories in a second port to the controller block.Type: GrantFiled: June 7, 2005Date of Patent: June 19, 2007Assignee: Sony CorporationInventors: Takashi Yamamoto, Kenichi Satori
-
Publication number: 20060184758Abstract: A storage device includes a plurality of memories storing data; and a controller controlling the memories, the controller performing in parallel in a number of the memories, the number being specified by a supplied specifying signal, one of a data writing process for writing data supplied from a connection destination device to which the storage device is connectable and a data reading process for reading data requested by the connection destination device.Type: ApplicationFiled: January 11, 2006Publication date: August 17, 2006Applicant: Sony CorporationInventors: Kenichi Satori, Keiichi Tsutsui, Kenichi Nakanishi, Hideaki Bando, Hideaki Okubo, Yoshitaka Aoki, Tamaki Konno
-
Publication number: 20060077583Abstract: The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage device 1, when data read processing is performed for the erase-processing applied area in a memory section 2 to read out erase-state actual data Ddr and erase-state parity data Ddp each containing only “1s”, the erase-state actual data Ddr and erase-state parity data Ddp are inverted by a third data inverting circuit 13 to make all the values thereof “0”, followed by execution of the error detection processing. With the above configuration, it is possible to prevent an error from being detected in the error detection processing.Type: ApplicationFiled: September 8, 2005Publication date: April 13, 2006Inventors: Kenichi Satori, Kenichi Nakanishi, Hideaki Bando, Takahiro Fukushige
-
Publication number: 20050281104Abstract: The present invention is intended to significantly enhance processing efficiency. The card-type semiconductor storage device has a first data communication line group for connecting nonvolatile memories in a first port to a controller block and a second data communication line group for connecting nonvolatile memories in a second port to the controller block.Type: ApplicationFiled: June 7, 2005Publication date: December 22, 2005Inventors: Takashi Yamamoto, Kenichi Satori
-
Publication number: 20050174857Abstract: A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.Type: ApplicationFiled: February 2, 2005Publication date: August 11, 2005Applicant: Sony CorporationInventors: Takahiro Fukushige, Kenichi Satori, Kenichi Nakanishi, Hideaki Bando, Junko Sasaki, Kunihiko Miura, Toshinori Nakamura, Kensuke Hatsukawa
-
Patent number: 6847554Abstract: A semiconductor memory device for error correction encoding and decoding able to avoid erroneous judgment occurring due to erroneous correction when a nonvolatile memory is in a predetermined initial state, wherein, at the time of writing, write data and predetermined status data, for example, erasure data when the nonvolatile memory is in an erasure state are compared and, when the result of the comparison is that the write data coincides with the erasure data, the erasure data is selected and, conversely when they do not coincide, the encoded data obtained by error correction encoding the write data is selected and written into the nonvolatile memory, while at the time of reading, when the result of the comparison between the read data and the erasure data from the nonvolatile memory is that the read data coincides with the erasure data, the erasure data is selected and, conversely when they do not coincide, the decoded data obtained by error correction decoding the read data is selected and output.Type: GrantFiled: July 31, 2003Date of Patent: January 25, 2005Assignee: Sony CorporationInventor: Kenichi Satori
-
Publication number: 20040022087Abstract: A semiconductor memory device for error correction encoding and decoding able to avoid erroneous judgment occurring due to erroneous correction when a nonvolatile memory is in a predetermined initial state, wherein, at the time of writing, write data and predetermined status data, for example, erasure data when the nonvolatile memory is in an erasure state are compared and, when the result of the comparison is that the write data coincides with the erasure data, the erasure data is selected and, conversely when they do not coincide, the encoded data obtained by error correction encoding the write data is selected and written into the nonvolatile memory, while at the time of reading, when the result of the comparison between the read data and the erasure data from the nonvolatile memory is that the read data coincides with the erasure data, the erasure data is selected and, conversely when they do not coincide, the decoded data obtained by error correction decoding the read data is selected and output.Type: ApplicationFiled: July 31, 2003Publication date: February 5, 2004Inventor: Kenichi Satori
-
Patent number: 5822248Abstract: A non-volatile memory device which enables use of a folded bit line system includes odd and even main bit lines, a plurality of sub-bit lines connected to the main bit lines through selection gates. Conductive and non-conductive states of the selection gate connecting to the odd main bit line and the selection gate connecting to the even main bit line are controlled by different selection signal lines so that the odd main bit line and the even bit line are operated selectively.Type: GrantFiled: November 17, 1995Date of Patent: October 13, 1998Assignee: Sony CorporationInventors: Kenichi Satori, Hiromi Nobukata