Patents by Inventor Kenichi Sawada

Kenichi Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230026414
    Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.
    Type: Application
    Filed: October 3, 2022
    Publication date: January 26, 2023
    Applicants: KIOXIA CORPORATION, SK HYNIX INC.
    Inventors: Taiga ISODA, Eiji KITAGAWA, Young Min Min EEH, Tadaaki OIKAWA, Kazuya SAWADA, Kenichi YOSHINO, Jong Koo LIM, Ku Youl JUNG, Guk Cheon Cheon KIM
  • Publication number: 20220395919
    Abstract: A gear manufacturing apparatus for machining a gear workpiece wherein, when at least one of end regions in a tooth trace direction of each tooth of the workpiece is machined, a control device executes a specific machining control for adjusting a relative position of a tool to the workpiece based on information about the relative position computed by setting, as a machining reference position, a position of the tool on an outer edge line in an X-axis-orthogonal cross section different from a normal machining point such that a distance between a center of the tool and a center of the gear workpiece in the X-axis-orthogonal cross section when the at least one of the end regions is machined is larger than when the at least one of the end regions is machined by setting the normal machining point as the machining reference position.
    Type: Application
    Filed: March 29, 2022
    Publication date: December 15, 2022
    Applicant: YUTAKA GEARS AND MACHINERY CORP.
    Inventors: Yoshiki TANIMOTO, Norikazu SAWADA, Kenichi MARUYAMA, Ryouta MURAKAMI
  • Patent number: 11495740
    Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 8, 2022
    Assignees: KIOXIA CORPORATION, SK HYNIX INC.
    Inventors: Taiga Isoda, Eiji Kitagawa, Young Min Eeh, Tadaaki Oikawa, Kazuya Sawada, Kenichi Yoshino, Jong Koo Lim, Ku Youl Jung, Guk Cheon Kim
  • Patent number: 11445785
    Abstract: Provided is a shoe sole member partially or entirely formed of a resin composite, the resin composite including; a non-foamed elastic body matrix composed of an elastomer; and a plurality of resin foam particles dispersed in the elastic body matrix. Also provided is a shoe including the shoe sole member.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 20, 2022
    Assignee: ASICS CORPORATION
    Inventors: Junichiro Tateishi, Takashi Yamade, Daisuke Sawada, Takashi Osaki, Kenichi Harano
  • Patent number: 11417591
    Abstract: A semiconductor module includes: a circuit board; a semiconductor chip having a first electrode pad on a first surface, bonded to the circuit board at a second surface that is opposite to the first surface, and having side surfaces intersecting the first surface and the second surface; an external terminal electrically connected to the first electrode pad; and an insulating member configured to fix the external terminal, wherein by the insulating member contacting the side surfaces of the semiconductor chip at a plurality of locations, parallel movement and rotational movement of the semiconductor chip relative to the insulating member in a plane parallel, to the first surface are restricted, and wherein the external terminal penetrates the insulating member.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: August 16, 2022
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kenichi Sawada, Jiro Shinkai, So Tanaka, Hirotaka Oomori
  • Publication number: 20220253141
    Abstract: Provided is a vibration device that is connected to an information processing apparatus and includes a vibration mechanism that generates a vibration. The vibration device receives a first vibration command for the vibration device from the information processing apparatus, receives a second vibration command for a different type of vibration device from the information processing apparatus in parallel with the first vibration command, and operates the vibration mechanism on the basis of at least one of the first vibration command and the second vibration command. The second vibration command is in a format different from that of the first vibration command. The different type of vibration device is of a type different from that of the vibration device.
    Type: Application
    Filed: June 16, 2020
    Publication date: August 11, 2022
    Inventors: Takashi ENOKIHARA, Takuro SAWADA, Masatoshi NAKAE, Shinya MIKAMI, Kenichi SATO, Yoshiyuki IMADA
  • Patent number: 11404211
    Abstract: A mounting structure of a multilayer ceramic capacitor includes a multilayer ceramic capacitor and a mounting substrate on which the multilayer ceramic capacitor is mounted. The multilayer ceramic capacitor includes a laminate including a plurality of dielectric layers and a plurality of internal electrodes alternately laminated, and a first external electrode, a second external electrode, a third external electrode, and a fourth external electrode provided on a surface of the laminate. The plurality of internal electrodes include a first internal electrode, a second internal electrode, and a third internal electrode. The first external electrode, the third external electrode, and the fourth external electrode are bonded to the mounting substrate, and current is not directly supplied from the mounting substrate to the second external electrode.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: August 2, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenichi Togou, Takashi Sawada
  • Publication number: 20220238792
    Abstract: A magnetic memory device includes a substrate; a first magnetoresistive effect element; and a second magnetoresistive effect element provided at a side of the first magnetoresistive effect element opposite to a side of the first magnetoresistive effect element at which the substrate is provided. A heat absorption rate of the first magnetoresistive effect element is lower than a heat absorption rate of the second magnetoresistive effect element.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: Kioxia Corporation
    Inventors: Kazuya SAWADA, Young Min EEH, Eiji KITAGAWA, Taiga ISODA, Tadaaki OIKAWA, Kenichi YOSHINO
  • Patent number: 11217512
    Abstract: A semiconductor module includes a semiconductor chip having a first surface provided with a first electrode pad and a second surface, opposite to the first surface, provided with a second electrode pad, a first substrate connected to the first electrode pad, a second substrate provided on the side of the second surface, and a conductor section, electrically connecting the second electrode pad and the second substrate, and having a size greater than the second electrode pad in a plan view viewed from the side of the second substrate.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: January 4, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kenichi Sawada, Jiro Shinkai
  • Publication number: 20210013130
    Abstract: A semiconductor module includes: a circuit board; a semiconductor chip having a first electrode pad on a first surface, bonded to the circuit board at a second surface that is opposite to the first surface, and having side surfaces intersecting the first surface and the second surface; an external terminal electrically connected to the first electrode pad; and an insulating member configured to fix the external terminal, wherein by the insulating member contacting the side surfaces of the semiconductor chip at a plurality of locations, parallel movement and rotational movement of the semiconductor chip relative to the insulating member in a plane parallel, to the first surface are restricted, and wherein the external terminal penetrates the insulating member.
    Type: Application
    Filed: January 22, 2019
    Publication date: January 14, 2021
    Inventors: Kenichi SAWADA, Jiro SHINKAI, So TANAKA, Hirotaka OOMORI
  • Publication number: 20200321271
    Abstract: A semiconductor module includes a semiconductor chip having a first surface provided with a first electrode pad and a second surface, opposite to the first surface, provided with a second electrode pad, a first substrate connected to the first electrode pad, a second substrate provided on the side of the second surface, and a conductor section, electrically connecting the second electrode pad and the second substrate, and having a size greater than the second electrode pad in a plan view viewed from the side of the second substrate.
    Type: Application
    Filed: August 23, 2018
    Publication date: October 8, 2020
    Inventors: Kenichi SAWADA, Jiro SHINKAI
  • Patent number: 10606531
    Abstract: An image processing device capable of executing a plurality of jobs that differ in kind, the image processing device includes: a controller that controls execution of an input job; and a detection part that, on the basis of a voice detected by a voice detector, detects that any of a plurality of predetermined target voices has been emitted, wherein in a case where it is detected that the target voice has been emitted during a target setting period corresponding to a job that is being executed, among setting periods that are defined beforehand according to kinds of jobs respectively, the controller stops the execution of the job.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 31, 2020
    Assignee: Konica Minolta, Inc.
    Inventors: Tomoko Maruyama, Kazuhiro Tomiyasu, Atsushi Tomita, Kenichi Sawada, Hiroshi Sugiura
  • Publication number: 20190141206
    Abstract: An image processing system includes: an image processing device that comprises a first display and a first hardware processor; and an information processing device that communicates with the image processing device, and comprises: a second display on which a second screen same as a first screen being displayed on the first display is displayed; and a second hardware processor, wherein one of the first and second hardware processors determines whether a screen display standard of the first display is left or right standard and whether a screen display standard of the second display is left or right standard, and inverts the second screen that is same as the first screen being displayed on the first display and is displayed on the second display right and left, when the screen display standards of the first and second displays are determined to be different from each other.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 9, 2019
    Applicant: Konica Minolta, Inc.
    Inventors: Atsushi Tomita, Kazuhiro Tomiyasu, Tomoko Maruyama, Kenichi Sawada, Hiroshi Sugiura
  • Publication number: 20190129665
    Abstract: An image processing device capable of executing a plurality of jobs that differ in kind, the image processing device includes: a controller that controls execution of an input job; and a detection part that, on the basis of a voice detected by a voice detector, detects that any of a plurality of predetermined target voices has been emitted, wherein in a case where it is detected that the target voice has been emitted during a target setting period corresponding to a job that is being executed, among setting periods that are defined beforehand according to kinds of jobs respectively, the controller stops the execution of the job.
    Type: Application
    Filed: October 22, 2018
    Publication date: May 2, 2019
    Applicant: KONICA MINOLTA, INC.
    Inventors: Tomoko Maruyama, Kazuhiro Tomiyasu, Atsushi Tomita, Kenichi Sawada, Hiroshi Sugiura
  • Patent number: 10275035
    Abstract: A device for determining a gesture includes a display portion for selectively displaying one of screens; a storage portion for storing, for each of the screens, a rule used for distinguishing between gestures; a detection portion for detecting a motion made by a user; and a determination portion for identifying, from among the gestures, a gesture represented by the motion detected by the detection portion based on the rule for a current screen, the current screen being one of the screens and being displayed at a time when the motion has been detected.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: April 30, 2019
    Assignee: Konica Minolta, Inc.
    Inventors: Hiroshi Sugiura, Hiroshi Iwamoto, Kenichi Sawada, Takeshi Hibino, Tomoko Maruyama
  • Patent number: 10228843
    Abstract: An image processing apparatus includes a display for displaying operational information for executing image processing, an operation unit for giving an input instruction in association with a display region appearing on the display, and a controller for controlling the display in accordance with the input instruction on the operation unit. The controller is configured to determine whether an input instruction of a flick operation is given through the operation unit in association with a prescribed display region appearing on the display. If it is determined that the input instruction of the flick operation is given, the controller is configured to enlarge a range of the prescribed display region in which the input instruction is allowed, and to display the enlarged display region on the display.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: March 12, 2019
    Assignee: KONICA MINOLTA BUSINESS TECHNOLOGIES, INC.
    Inventors: Yoichi Kurumasa, Kenichi Sawada, Masahiro Imamura, Atsushi Tomita, Tetsuya Tokumoto, Ryosuke Nishimura, Takatsugu Kuno
  • Patent number: 9966334
    Abstract: A semiconductor module (10A) according to one embodiment includes: vertical first and second transistor chips (12A, 12B), wherein a second main electrode pad (20) formed on a back surface of the first transistor chip is mounted on and connected to a first wiring pattern (74) on the substrate, a first control electrode pad (16) formed together with a first main electrode pad on a front surface of the first transistor chip is electrically connected to a second wiring pattern (76) on the substrate, third main electrode pad (18) formed together with a second control electrode pad on a front surface of the second transistor is mounted on and connected to the first wiring pattern, and the second control electrode pad (16) formed on a back surface of the second transistor chip is electrically connected to a third wiring pattern.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: May 8, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Kenichi Sawada
  • Patent number: 9947639
    Abstract: A semiconductor module (10A) according to one embodiment includes a plurality of first and second transistor chips (hereinafter, first and second transistors) (12A, 12B) and a substrate (90). In each of the first and second transistors, first and second main electrode pads (18, 20) are each electrically connected together; the second main electrode pads of the first transistors are electrically connected to the first main electrode pads of the second transistors; control electrode pads of the first and second transistors are respectively connected to first and second control electrode wiring patterns (94, 98) on the substrate via first and second resistance parts (13A, 13B); and the first and second resistance parts respectively have a plurality of first and second resistance elements (72A, 72B) each connected to the corresponding control electrode pad, and first and second linking parts (74A, 74B) respectively linking the plurality of first and second resistance elements together.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: April 17, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Kenichi Sawada
  • Publication number: 20170287828
    Abstract: A semiconductor module (10A) according to one embodiment includes: vertical first and second transistor chips (12A, 12B), wherein a second main electrode pad (20) formed on a back surface of the first transistor chip is mounted on and connected to a first wiring pattern (74) on the substrate, a first control electrode pad (16) formed together with a first main electrode pad on a front surface of the first transistor chip is electrically connected to a second wiring pattern (76) on the substrate, third main electrode pad (18) formed together with a second control electrode pad on a front surface of the second transistor is mounted on and connected to the first wiring pattern, and the second control electrode pad (16) formed on a back surface of the second transistor chip is electrically connected to a third wiring pattern.
    Type: Application
    Filed: September 2, 2015
    Publication date: October 5, 2017
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Kenichi Sawada
  • Publication number: 20170278824
    Abstract: A semiconductor module (10A) according to one embodiment includes a plurality of first and second transistor chips (hereinafter, first and second transistors) (12A, 12B) and a substrate (90). In each of the first and second transistors, first and second main electrode pads (18, 20) are each electrically connected together; the second main electrode pads of the first transistors are electrically connected to the first main electrode pads of the second transistors; control electrode pads of the first and second transistors are respectively connected to first and second control electrode wiring patterns (94, 98) on the substrate via first and second resistance parts (13A, 13B); and the first and second resistance parts respectively have a plurality of first and second resistance elements (72A, 72B) each connected to the corresponding control electrode pad, and first and second linking parts (74A, 74B) respectively linking the plurality of first and second resistance elements together.
    Type: Application
    Filed: September 2, 2015
    Publication date: September 28, 2017
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Kenichi Sawada