Abstract: Provided are suppressors of reduction of the blood-brain barrier (BBB) function, suppressors of the disruption of the tight junctions of the blood-brain barrier, suppressors of infiltration of leucocytes into the CNS, suppressors of permeation of IgGs in a patient's blood into the CNS, and therapeutic agents for neuromyelitis optica spectrum disorder, neuro-Behcet disease, neurosarcoidosis, central nervous system lupus (neuropsychiatric lupus), autoimmune encephalitis, or Vogt-Koyanagi-Harada disease which suppress reduction of blood-brain barrier function and/or restore reduced function of the blood-brain barrier, which contain an antibody containing a heavy chain variable region containing CDR1 having the sequence of SEQ ID NO: 1, CDR2 having the sequence of SEQ ID NO: 2, and CDR3 having the sequence of SEQ ID NO: 3, and a light chain variable region containing CDR1 having the sequence of SEQ ID NO: 4, CDR2 having the sequence of SEQ ID NO: 5, and CDR3 having the sequence of SEQ ID NO: 6.

Abstract: A semiconductor storage device precharging a bit line pair to a ground potential includes a sense amplifier connected between the bit line pair, a storage cell connected to one of the bit line pair and storing data, a first transistor controlling a conduction state between the other of the bit line pair and a reference cell node, a second transistor connected between a reference voltage source generating a reference voltage and the reference cell node, the second transistor exclusively controlled from the first transistor, and a capacitor setting a potential of the reference cell node.

Abstract: A semiconductor storage device precharging a bit line pair to a ground potential includes a sense amplifier connected between the bit line pair, a storage cell connected to one of the bit line pair and storing data, a first transistor controlling a conduction state between the other of the bit line pair and a reference cell node, a second transistor connected between a reference voltage source generating a reference voltage and the reference cell node, the second transistor exclusively controlled from the first transistor, and a capacitor setting a potential of the reference cell node.

Abstract: A semiconductor memory device in an SRAM using a 4 transistor-type memory cell which device includes an error writing protection circuit for preventing any information from being written into a memory cell into which any information is not needed to be written owing to line capacitance between adjacent bit lines. The error writing protection circuit includes an N-type transistors, a P-type transistor, and diodes. Hereby, it is determined whether or not a bit line is charged with electricity in accordance with electric potential of an adjacent bit line, and there is not charged with electricity a bit line for which there is no possibility of any information from being written, but there is charged with electricity only bit lines where there is possibility of any information being written in error. Thus, there is flowed no excess current.

Abstract: A semiconductor memory device includes a memory cell array, a read/write control circuit, a signal generator, and a write error prevention circuit. In the memory cell array, a plurality of memory cells are formed at intersections of pluralities of word lines and bit lines. The read/write control circuit controls a data read/write from/in the memory cell array in accordance with a mode setting signal representing a read/write mode, a data input signal, and an address signal. The signal generator generates a one-shot pulse signal when the mode setting signal represents a write mode. The write error prevention circuit precharges a bit line of the memory cell array by the one-shot pulse signal from the signal generator.